MAX1540A Datasheet, PDF (29/49 Pages) Maxim Integrated Products – Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator

Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
MOSFET Gate Drivers (DH_, DL_)
The DH_ and DL_ drivers are optimized for driving mod-
erate-sized high-side, and larger low-side power
MOSFETs. This is consistent with the low duty factor
seen in notebook applications where a large V_IN - V_OUT
differential exists. An adaptive dead-time circuit moni-
tors the DL_ output and prevents the high-side MOSFET
from turning on until DL_ is off. A similar adaptive dead-
time circuit monitors the DH_ output, preventing the low-
side MOSFET from turning on until DH_ is off. There
must be a low-resistance, low-inductance path from the
DL_ and DH_ drivers to the MOSFET gates for the adap-
tive dead-time circuits to work properly; otherwise, the
sense circuitry in the MAX1540A/MAX1541 interprets
the MOSFET gates as “off” while charge actually
remains. Use very short, wide traces (50 mils to 100 mils
wide if the MOSFET is 1in from the driver).
The internal pulldown transistor that drives DL_ low is
robust, with a 0.6Ω (typ) on-resistance. This helps pre-
vent DL_ from being pulled up due to capacitive cou-
pling from the drain to the gate of the low-side MOSFETs
when the inductor node (LX_) quickly switches from
ground to V_IN. Applications with high input voltages and
long inductive driver traces may require additional gate-
to-source capacitance to ensure fast-rising LX_ edges
do not pull up the low-side MOSFETs gate, causing
shoot-through currents. The capacitive coupling
between LX_ and DL_ created by the MOSFET’s gate-to-
drain capacitance (C_RSS), gate-to-source capacitance
(C_ISS-C_RSS), and additional board parasitics should not
exceed the following minimum threshold:
V_GS(TH)
>
V_IN
⎛
⎝⎜
C_RSS
C_ISS
⎞
⎠⎟
Lot-to-lot variation of the threshold voltage can cause
problems in marginal designs. Alternatively, adding a
resistor less than 10Ω in series with BST_ can remedy the
problem by increasing the turn-on time of the high-side
MOSFET without degrading the turn-off time (Figure 8).
POR, UVLO, and Soft-Start
Power-on reset (POR) occurs when V_CC rises above
approximately 2V, resetting the fault latch and soft-start
counter, powering-up the reference, and preparing the
PWM for operation. Until V_CC reaches 4.25V (typ), V_CC
undervoltage lockout (UVLO) circuitry inhibits switching.
The controller inhibits switching by pulling DH_ low, and
holding DL_ low when OVP and shutdown discharge are
disabled or forcing DL_ high when OVP and shutdown
discharge are enabled (Table 7). When V_CC rises above
4.25V and ON_ is driven high, the controller activates the
PWM controller and initializes soft-start.
V_DD
MAX1540A
MAX1541
BST
DH
LX
V_DD
DL
PGND
(R_BST)*
C_BST
(C_NL)*
C_BYP
D_BST
INPUT (V_IN)
N_H
L
N_L
(R_BST)* OPTIONAL—THE RESISTOR LOWERS EMI BY DECREASING
THE SWITCHING NODE RISE TIME.
(C_NL)* OPTIONAL—THE CAPACITOR REDUCES LX TO DL CAPACITIVE
COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS.
Figure 8. Optional Gate-Driver Circuitry
Soft-start allows a gradual increase of the internal current-
limit level during startup to reduce the input surge cur-
rents. The MAX1540A/MAX1541 divide the soft-start
period into five phases. During the first phase, the con-
troller limits the current limit to only 20% of the full current
limit. If the output does not reach regulation within 425µs,
soft-start enters the second phase, and the current limit is
increased by another 20%. This process is repeated until
the maximum current limit is reached after 1.7ms or when
the output reaches the nominal regulation voltage,
whichever occurs first (see the soft-start waveforms in the
Typical Operating Characteristics).
Power-Good Output (PGOOD_)
PGOOD_ is the open-drain output for a window com-
parator that continuously monitors the output. PGOOD_
is actively held low in shutdown and during soft-start.
After the digital soft-start terminates, PGOOD_ becomes
high impedance as long as the respective output volt-
age is within ±10% of the nominal regulation voltage set
by FB_. When the output voltage drops 10% below or
rises 10% above the nominal regulation voltage, the
MAX1540A/MAX1541 pull the respective power-good
output (PGOOD_) low by turning on the MOSFET
(Figure 9). Any fault condition forces both PGOOD1 and
PGOOD2 low until the fault latch is cleared by toggling
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