MAX1540A Datasheet, PDF (41/49 Pages) Maxim Integrated Products – Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator

Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
A reasonable minimum value for h is 1.5, but adjusting
this up or down allows trade-offs between V_SAG, output
capacitance, and minimum operating voltage. For a
given value of h, the minimum operating voltage can be
calculated as:
V_IN(MIN) =
V_OUT + V_DROP1
1-
⎛
⎝⎜
h
×
t_OFF(MIN)
K
⎞
⎠⎟
where V_DROP1 is the parasitic voltage drop in the
charge path (see the On-Time One-Shot (TON) section),
t_OFF(MIN) is from the Electrical Characteristics, and K is
taken from Table 3. The absolute minimum input voltage
is calculated with h = 1.
If the calculated V_IN(MIN) is greater than the required
minimum input voltage, then operating frequency must
be reduced or output capacitance added to obtain an
acceptable V_SAG. If operation near dropout is anticipat-
ed, calculate V_SAG to be sure of adequate transient
response.
• V_OUT2 = 2.5V
Dropout Design Example
• f_SW = 355kHz
• K = 3.0µs, worst-case K_MIN = 3.3µs
• t_OFF(MIN) = 500ns
• V_DROP1 = 100mV
• h = 1.5
V_IN(MIN) =
2.5V + 0.1V
1-
⎛
⎝⎜
1.5 × 500ns
3.0μs
⎞
⎠⎟
= 3.47V
Calculating again with h = 1 and the typical K-factor
value (K = 3.3µs) gives the absolute limit of dropout:
V_IN(MIN) =
2.5V + 0.1V
1-
⎛
⎝⎜
1× 500ns
3.3μs
⎞
⎠⎟
= 3.06V
Therefore, V_IN must be greater than 3.06V, even with
very large output capacitance, and a practical input volt-
age with reasonable output capacitance would be 3.47V.
Multi-Output Voltage Settings
(MAX1541 OUT1 Only)
While the main MAX1541 controller (OUT1) is optimized
to work with applications that require two dynamic out-
put voltages, it can produce three or more output volt-
ages if required by using discrete logic or a DAC.
Figure 15 shows an application circuit providing four
voltage levels using discrete logic. Switching resistors
in and out of the resistor network changes the voltage
at REFIN1. An edge-detection circuit is added to gen-
erate a 1µs pulse on GATE to trigger the fault blanking
and forced-PWM operation. When using PWM mode
(SKIP = V_CC or open) on the main controller, the edge-
detection circuit is only required if fault blanking is
enabled. Otherwise, leave OD unconnected.
Active Bus Termination
(MAX1541 OUT1 Only)
Active-bus-termination power supplies generate a volt-
age rail that tracks a set reference. They are required to
source and sink current. DDR memory architecture
requires active bus termination. In DDR memory archi-
tecture, the termination voltage is set at exactly half the
memory supply voltage. Configure the main MAX1541
controller (OUT1) to generate the termination voltage
using a resistive voltage-divider at REFIN1. In such an
application, the main MAX1541 controller (OUT1) must
be kept in PWM mode (SKIP = V_CC or open) in order
for it to source and sink current. Figure 16 shows the
main MAX1541 controller configured as a DDR termina-
tion regulator. Connect GATE and FBLANK to GND
when unused.
REF
R4
R1
REFIN1
B
A
R3 _C1
R2
MAX1541
GND
1.5kΩ
1000pF
GATE
1.5kΩ
1000pF
Figure 15. Multi-Output Voltage Settings
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