MAX1544 Datasheet, PDF (37/42 Pages) Maxim Integrated Products – Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies

Dual-Phase, Quick-PWM Controller for
AMD Hammer CPU Core Power Supplies
Applications Information
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low
switching losses and clean, stable operation. The
switching power stage requires particular attention
(Figure 11). If possible, mount all of the power compo-
nents on the topside of the board with their ground ter-
minals flush against one another. Follow these
guidelines for good PC board layout:
1) Keep the high-current paths short, especially at
the ground terminals. This is essential for stable,
jitter-free operation.
2) Connect all analog grounds to a separate solid
copper plane, which connects to the GND pin of
the Quick-PWM controller. This includes the V_CC
bypass capacitor, REF and GNDS bypass capaci-
tors, compensation (CC_) components, and the
resistive dividers connected to ILIM and OFS.
3) Each slave controller should also have a separate
analog ground. Return the appropriate noise-sen-
sitive slave components to this plane. Since the
reference in the master is sometimes connected
to the slave, it may be necessary to couple the
analog ground in the master to the analog ground
in the slave to prevent ground offsets. A low-value
(≤10Ω) resistor is sufficient to link the two grounds.
4) Keep the power traces and load connections short.
This is essential for high efficiency. The use of thick
copper PC boards (2oz vs. 1oz) can enhance full-
load efficiency by 1% or more. Correctly routing PC
board traces is a difficult task that must be
approached in terms of fractions of centimeters,
where a single mΩ of excess trace resistance
causes a measurable efficiency penalty.
5) Keep the high-current, gate-driver traces (DL, DH,
LX, and BST) short and wide to minimize trace
resistance and inductance. This is essential for
high-power MOSFETs that require low-impedance
gate drivers to avoid shoot-through currents.
6) C_P, C_N, OAIN+, and OAIN- connections for cur-
rent limiting and voltage positioning must be made
using Kelvin-sense connections to guarantee the
current-sense accuracy.
7) When trade-offs in trace lengths must be made, it
is preferable to allow the inductor-charging path to
be made longer than the discharge path. For
example, it is better to allow some extra distance
between the input capacitors and the high-side
MOSFET than to allow distance between the
inductor and the low-side MOSFET or between the
inductor and the output filter capacitor.
8) Route high-speed switching nodes away from
sensitive analog areas (REF, CCV, CCI, FB, C_P,
C_N, etc). Make all pin-strap control input connec-
tions (SHDN, ILIM, SKIP, SUS, S_, TON) to analog
ground or V_CC rather than power ground or V_DD.
Layout Procedure
Place the power components first, with ground termi-
nals adjacent (low-side MOSFET source, C_IN, C_OUT,
and D1 anode). If possible, make all these connections
on the top layer with wide, copper-filled areas.
1) Mount the controller IC adjacent to the low-side
MOSFET. The DL gate traces must be short and
wide (50 mils to 100 mils wide if the MOSFET is
1in from the controller IC).
2) Group the gate-drive components (BST diodes
and capacitors, V_DD bypass capacitor) together
near the controller IC.
3) Make the DC-to-DC controller ground connections
as shown in the Standard Application Circuits.
This diagram can be viewed as having four sepa-
rate ground planes: input/output ground, where all
the high-power components go; the power ground
plane, where the PGND pin and V_DD bypass
capacitor go; the master’s analog ground plane,
where sensitive analog components, the master’s
GND pin, and V_CC bypass capacitor go; and the
slave’s analog ground plane, where the slave’s
GND pin and V_CC bypass capacitor go. The mas-
ter’s GND plane must meet the PGND plane only
at a single point directly beneath the IC. Similarly,
the slave’s GND plane must meet the PGND plane
only at a single point directly beneath the IC. The
respective master and slave ground planes
should connect to the high-power output ground
with a short metal trace from PGND to the source
of the low-side MOSFET (the middle of the star
ground). This point must also be very close to the
output capacitor ground terminal.
4) Connect the output power planes (V_CORE and
system ground planes) directly to the output filter
capacitor positive and negative terminals with
multiple vias. Place the entire DC-to-DC converter
circuit as close to the CPU as is practical.
Chip Information
TRANSISTOR COUNT: 11,015
PROCESS: BiCMOS
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