MAX1544 Datasheet, PDF (20/42 Pages) Maxim Integrated Products – Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies

Dual-Phase, Quick-PWM Controller for
AMD Hammer CPU Core Power Supplies
Table 3. Operating Mode Truth Table
SHDN
SUS
SKIP
OFS
OUTPUT
VOLTAGE
GND
x
x
x
GND
V_CC
GND
V_CC
GND or REF
D0–D4
(No offset)
V_CC
x
GND
or
REF
GND or REF
D0–D4
(No offset)
OPERATING MODE
Low-Power Shutdown Mode. DL_ is forced high, DH_ is
forced low, and the PWM controller is disabled. The supply
current drops to 1µA (typ).
Normal Operation. The no-load output voltage is determined by
the selected VID DAC code (D0–D4, Table 4).
Pulse-Skipping Operation. When SKIP is pulled low, the
MAX1544 immediately enters pulse-skipping operation
allowing automatic PWM/PFM switchover under light loads.
The VROK upper threshold is blanked.
V_CC
GND
x
0 to 0.8V
or
1.2V to 2V
D0–D4
(Plus offset)
Deep-Sleep Mode. The no-load output voltage is determined
by the selected VID DAC code (D0–D4, Table 4) plus the
offset voltage set by OFS.
REF
V_CC
or
x
High
V_CC
x
x
x
SUS, S0–S1
(No offset)
Suspend Mode. The no-load output voltage is determined by
the selected suspend code (SUS, S0–S1, Table 5),
overriding all other active modes of operation.
Fault Mode. The fault latch has been set by either UVP, OVP,
x
GND
or thermal shutdown. The controller remains in FAULT mode
until V_CC power is cycled or SHDN toggled.
This eliminates the need for the Schottky diode normally
connected between the output and ground to clamp the
negative output voltage excursion. When the DAC
reaches the 0V setting, DL_ goes high, DH_ goes low,
the reference turns off, and the supply current drops to
about 1µA. When a fault condition—output undervoltage
lockout, output overvoltage lockout (OVP = V_CC), or ther-
mal shutdown—activates the shutdown sequence, the
controller sets the fault latch to prevent the controller from
restarting. To clear the fault latch and reactivate the con-
troller, toggle SHDN or cycle V_CC power below 1V.
When SHDN goes high, the reference powers up. Once
the reference voltage exceeds its UVLO threshold, the
controller evaluates the DAC target and starts switching.
The slew-rate controller ramps up from 0V in LSB
increments to the currently selected output-voltage set-
ting (see the Power-Up Sequence section). There is no
traditional soft-start (variable current-limit) circuitry, so
full output current is available immediately.
Internal Multiplexers
The MAX1544 has a unique internal DAC input
multiplexer (muxes) that selects one of three different
DAC code settings for different processor states
(Figure 3). On startup, the MAX1544 selects the DAC
code from the D0–D4 (SUS = GND) or S0–S1 (SUS = REF
or high) input decoders.
DAC Inputs (D0–D4)
During normal forced-PWM operation (SUS = GND), the
digital-to-analog converter (DAC) programs the output
voltage using the D0–D4 inputs. Do not leave D0–D4
unconnected. D0–D4 can be changed while the
MAX1544 is active, initiating a transition to a new output
voltage level. Change D0–D4 together, avoiding
greater than 1µs skew between bits. Otherwise, incor-
rect DAC readings can cause a partial transition to the
wrong voltage level followed by the intended transition
to the correct voltage level, lengthening the overall tran-
sition time. The available DAC codes and resulting out-
put voltages are compatible with AMD Hammer voltage
specifications (Table 4).
Four-Level Logic Inputs
TON and S0–S1 are four-level logic inputs. These
inputs help expand the functionality of the controller
without adding an excessive number of pins. The four-
level inputs are intended to be static inputs. When left
open, an internal resistive voltage-divider sets the input
voltage to approximately 3.5V. Therefore, connect the
four-level logic inputs directly to V_CC, REF, or GND
when selecting one of the other logic levels. See the
Electrical Characteristics for exact logic level voltages.
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