MAX1544 Datasheet, PDF (14/42 Pages) Maxim Integrated Products – Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies

Dual-Phase, Quick-PWM Controller for
AMD Hammer CPU Core Power Supplies
Pin Description
PIN
NAME
FUNCTION
1
TIME
Slew-Rate Adjustment Pin. Connect a resistor from TIME to GND to set the internal slew-rate clock. A
150kΩ to 15kΩ resistor sets the clock from 100kHz to 1MHz, f_SLEW = 500kHz × 30kΩ/R_TIME.
On-Time Selection Control Input. This four-level input sets the K-factor value used to determine the
2
TON
DH_ on-time (see the On-Time One-Shot (T_ON) section): GND = 550kHz, REF = 300kHz, OPEN =
200kHz, V_CC = 100kHz
Suspend Input. SUS is a three-level logic input. When the controller detects on-transition on SUS, the
controller slews the output voltage to the new voltage level determined by SUS, S0–S1, and D0–D4.
The controller blanks VROK during the transition and another 24 R_TIME clock cycles after the new
3
SUS
DAC code is reached. Connect SUS as follows to select which multiplexer sets the nominal output
voltage:
3.3V or V_CC (high) = Suspend mode; S0–S1 low-range suspend code (Table 5)
REF = Suspend mode; S0–S1 high-range suspend code (Table 5)
GND = Normal operation; D0–D4 VID DAC code (Table 4)
Suspend-Mode Voltage Select Inputs. S0–S1 are four-level digital inputs that select the suspend
4, 5
S0, S1
mode VID code (Table 5) for the suspend mode multiplexer inputs. If SUS is high, the suspend mode
VID code is delivered to the DAC (see the Internal Multiplexers section), overriding any other voltage
setting (Figure 3).
Shutdown Control Input. This input cannot withstand the battery voltage. Connect to V_CC for normal
operation. Connect to ground to put the IC into its 1µA (typ) shutdown state. During the transition from
6
SHDN
normal operation to shutdown, the output voltage ramps down at 4 times the output-voltage slew rate
programmed by the TIME pin. In shutdown mode, DLM and DLS are forced to V_DD to clamp the output to
ground. Forcing SHDN to 12V ~ 15V disables both overvoltage protection and undervoltage protection
circuits, disables overlap operation, and clears the fault latch. Do not connect SHDN to >15V.
Voltage-Divider Input for Offset Control. For 0 < V_OFS < 0.8V, 0.125 times the voltage at OFS is
7
OFS
subtracted from the output. For 1.2V < V_OFS < 2V, 0.125 times the difference between REF and OFS
is added to the output. Voltages in the range of 0.8V < V_OFS < 1.2V are undefined. The controller
disables the offset amplifier during suspend mode (SUS = REF or high).
2V Reference Output. Bypass to GND with 0.22µF or greater ceramic capacitor. The reference can
8
REF
source 100µA for external loads. Loading REF degrades output voltage accuracy according to the
REF load regulation error.
Current-Limit Adjustment. The current-limit threshold defaults to 30mV if ILIM is tied to V_CC. In
9
ILIM
adjustable mode, the current-limit threshold voltage is precisely 1/20 the voltage seen at ILIM over a
0.2V to 1.5V range. The logic threshold for switchover to the 30mV default value is approximately V_CC
- 1V.
Analog Supply Voltage Input for PWM Core. Connect V_CC to the system supply voltage (4.5V to 5.5V)
10
V_CC
with a series 10Ω resistor. Bypass to GND with a 1µF or greater ceramic capacitor, as close to the IC
as possible.
11
GND
Analog Ground. Connect the MAX1544’s exposed pad to analog ground.
12
CCV
Voltage Integrator Capacitor Connection. Connect a 47pF to 1000pF (47pF typ) capacitor from CCV
to analog ground (GND) to set the integration time constant.
Ground Remote-Sense Input. Connect GNDS directly to the CPU ground-sense pin. GNDS internally
13
GNDS connects to an amplifier that adjusts the output voltage, compensating for voltage drops from the
regulator ground to the load ground.
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