MAX1544 Datasheet, PDF (21/42 Pages) Maxim Integrated Products – Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies

Dual-Phase, Quick-PWM Controller for
AMD Hammer CPU Core Power Supplies
D0–D4
DECODER
D0
D1
D2
IN
SUSPEND
MUX
D3
OUT
0
D4
S0–S1
DECODER
S0
IN
S1
OUT
1
OUT
DAC
SEL
SEL
SUS
2.5V
1.0V
SUS 3-LEVEL
DECODER
Figure 3. Internal Multiplexers Functional Diagram
Suspend Mode
When the processor enters low-power suspend mode, it
sets the regulator to a lower output voltage to reduce
power consumption. The MAX1544 includes independent
suspend-mode output voltage codes set by the four-level
S0–S1 inputs and the three-level SUS input. When the
CPU suspends operation (SUS = REF or high), the con-
troller disables the offset amplifier and overrides the 5-bit
VID DAC code set by either D0–D4 (normal operation).
The master controller slews the output to the selected
suspend-mode voltage. During the transition, the
MAX1544 blanks VROK and the UVP fault protection until
24 R_TIME clock cycles after the slew-rate controller reach-
es the suspend-mode voltage.
SUS is a three-level logic input: GND, REF, or high. This
expands the functionality of the controller without
adding an additional pin. This input is intended to be
driven by a dedicated open-drain output with the pullup
resistor connected either to REF (or a resistive divider
from V_CC) or to a logic-level bias supply (3.3V or
greater). When pulled up to REF, the MAX1544 selects
the upper suspend voltage range. When pulled high
(2.7V or greater), the controller selects the lower sus-
pend voltage range. See the Electrical Characteristics
for exact logic level voltages.
Output Voltage Transition Timing
The MAX1544 is designed to perform mode transitions in
a controlled manner, automatically minimizing input surge
currents. This feature allows the circuit designer to
achieve nearly ideal transitions, guaranteeing just-in-time
arrival at the new output voltage level with the lowest pos-
sible peak currents for a given output capacitance.
At the beginning of an output voltage transition, the
MAX1544 blanks the VROK output, preventing it from
changing states. VROK remains blanked during the
transition and is enabled 24 clock cycles after the
slew-rate controller has set the final DAC code value.
The slew-rate clock frequency (set by resistor R_TIME)
must be set fast enough to ensure that the transition is
completed within the maximum allotted time.
The slew-rate controller transitions the output voltage in
25mV steps during soft-start, soft-shutdown, and sus-
pend-mode transitions. The total time for a transition
depends on R_TIME, the voltage difference, and the
accuracy of the MAX1544’s slew-rate clock, and is not
dependent on the total output capacitance. The greater
the output capacitance, the higher the surge current
required for the transition. The MAX1544 automatically
controls the current to the minimum level required to
complete the transition in the calculated time, as long
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