MAX14826 Datasheet, PDF (28/32 Pages) Maxim Integrated Products – IO-Link Device Transceiver

MAX14826
IO-Link Device Transceiver
SPI Interface
The device communicates through an SPI-compatible
4-wire serial interface when SPI/PAR is high. The inter-
face has three inputs—clock (SCLK/CQPP), chip select
(CS/PNP), and data in (SDI/DOPP)—and one data out
(SDO/DOOC). The maximum SPI clock rate for the device
is 12MHz. The SPI interface complies with clock polarity
CPOL = 0 and clock phase CPHA = 0 (see Figure 12 and
Figure 13).
The SPI interface is not available when V₅ or V_L are not
present.
CS/PNP
SCLK/CQPP
SDI/DOPP
W
0
0
0
0
0
R1
R0
D7
D6
D5
D4
D3
D2
D1
D0
R_ = REGISTER ADDRESS
D_ = DATA BIT
= CLOCK EDGE THAT INITIATES LATCHING OF SDI DATA
Figure 12. SPI Write Cycle
CS/PNP
SCLK/CQPP
SDI/DOPP X
R
0
0
0
0
0
R1 R0
X
SDO/DOOC
R_ = REGISTER ADDRESS
D_ = DATA BIT
= CLOCK EDGE THAT INITIATES LATCHING OF SDI DATA
= CLOCK EDGE THAT INITIATES WRITING OF SDO DATA
Figure 13. SPI Write Cycle
D7
D6
D5 D4
D3 D2 D1
D0
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