MAX14826 Datasheet, PDF (15/32 Pages) Maxim Integrated Products – IO-Link Device Transceiver

MAX14826
IO-Link Device Transceiver
Pin Configuration
TOP VIEW
18 17 16 15 14
DI ¹⁹
GND ²⁰
*EP
C/Q ²¹
DO ²²
MAX14826
VCC 23
+
VP 24
12345
13
12 _TX
11 DODIS
10 SPI/PAR
9 _VL
8 SDI/DOPP
7 SDO/DOOC
6
TQFN
4mm x 4mm
*Exposed Pad. Connect to GND.
Pin Description
PIN
NAME
FUNCTION
5V Linear Regulator Input. Bypass LDOIN to GND with a 1µF ceramic capacitor. LDOIN can be powered
1
LDOIN
from V_P or from an external source in the 7V to 36V range. If using V_P to power the LDO, connect LDOIN
to V_P through a 10W resistor.
5V Power-Supply Input and 5V Linear Regulator Output. Bypass V₅ to GND with a 0.1µF ceramic
2
V₅
capacitor for 10mA load capability. Add the recommended compensation network to increase the source
capability to 30mA. See the 5V and 3.3V Linear Regulators section for more information.
3
LDO33
3.3V Linear Regulator Output. Bypass LDO33 to GND with a 1µF ceramic capacitor.
Interrupt Request Output C/Q Overcurrent Indicator. In SPI mode, IRQ/CQOC is a standard active-low
4
IRQ/CQOC interrupt request output activated by the bits in the Status register. In parallel mode, IRQ/CQOC pulses
low when an overcurrent condition occurs on C/Q. IRQ/CQOC is a push-pull output referenced to V_L.
5
SCLK/CQPP
SPI Clock Input C/Q Mode Select Input. In SPI mode, SCLK/CQPP is the SPI clock input. In parallel
mode, SCLK/CQPP sets the configuration of the C/Q driver.
6
CS/PNP
Active-Low SPI Chip-Select Input C/Q and DO Mode Select Input. In SPI mode, CS/PNP is the SPI chip-
select input.In parallel mode, CS/PNP set the configuration for the C/Q and DO drivers.
7
SDO/DOOC
SPI Serial-Data Output/DO Overcurrent Indicator. In SPI mode, SDO/DOOC the SPI serial-data output. In
parallel mode, SDO/DOOC pulses low when an overcurrent condition occurs on DO.
8
SDI/DOPP
SPI Serial-Data Input/ DO Mode Select Input. In SPI mode, SDI/DOPP is the SPI serial data input. In
parallel mode, SDI/DOPP sets the configuration of the DO driver.
9
V_L
Logic-Level Supply Input. V_L defines the logic levels on all the logic inputs and outputs. Bypass V_L to
GND with a 0.1µF ceramic capacitor.
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