MAX14826 Datasheet, PDF (22/32 Pages) Maxim Integrated Products – IO-Link Device Transceiver

MAX14826
IO-Link Device Transceiver
BIT
NAME
DESCRIPTION
C/Q Logic Level. The QLvl bit is the inverse of the logic level at C/Q. QLvl is 1 when the
D4
QLvl
C/Q input level is low (< 8V) and is 0 when the C/Q logic level is high (> 13V) (Table 3).
QLvl remains active when the C/Q receiver output, RX is disabled (RxDis = 1). QLvl does
not affect IRQ/CQOC. QLvl is not changed when the Status register is read.
C/Q Fault Interrupt. The C/QFaultInt interrupt bit and C/QFault bit (in the Mode register)
D3
C/QFaultInt
are set when a short-circuit or voltage fault occurs on the C/Q driver output (see the C/Q
Fault Detection section for more information). IRQ/CQOC asserts when C/QFault is 1.
Read the Status register to clear the C/QFaultInt bit and deassert IRQ/CQOC.
Internal 3.3V LDO (LDO33) Undervoltage Warning. Both the UV33Int interrupt bit and
the UV33En bit (in the Mode register) are set when V_LDO33 falls below the 2.4V LDO33
undervoltage threshold. If UV33En is set in the Mode register, IRQ/CQOC asserts low
D2
UV33Int
when the UV33Int bit is 1. Read the Status register to clear the UV33Int bit and deassert
IRQ/CQOC. Set the UV33En bit to 1 in the Mode register to enable undervoltage
monitoring for UV33Int. When enabled, UV asserts high when the UV33Int bit is 1. UV
deasserts when V_LDO33 rises above the LDO33 undervoltage threshold.
V_CC Undervoltage Interrupt. The UV24Int interrupt bit and the UV24 bit (in the Mode
D1
UV24Int
register) are set when the V_CC voltage falls below the 7.4V undervoltage threshold.
IRQ/CQOC asserts low when the UV24Int bit is 1. Read the Status register to clear the
UV24Int bit and deassert IRQ/CQOC. V_CC undervoltage detection cannot be disabled.
Overtemperature Warning. The OTempInt interrupt bit and the OTemp bit (in the Mode
register) are set when a high-temperature condition is detected by the devices. OTemp
is set when the temperature of the die exceeds +127°C (typ). OTempInt is set and IRQ/
D0
OTempInt
CQOC asserts when the OTemp bit is 1. The OTempInt bit is cleared and IRQ/CQOC
deasserts when the Status register is read.
Once cleared, OTempInt is not reset if the die temperature remains above the thermal
warning threshold and does not fall below +104°C.
Table 3. DiLvl and LI Output
V_DI (V)
< 5.2
>8
DiLvl BIT
0
1
LI OUTPUT
High
Low
Table 4. QLvl and RX Output
V_C/Q (V)
<8
>13
QLvl BIT
1
0
RX OUTPUT
High
Low
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