MAX14826 Datasheet, PDF (21/32 Pages) Maxim Integrated Products – IO-Link Device Transceiver

MAX14826
IO-Link Device Transceiver
Register Functionality
The devices have four 8-bit-wide registers for configuration and monitoring (Table 2).
Table 2. Register Summary
REGISTER R1 R0
Status
00
CQConfig 0 1
DIOConfig 1 0
Mode
11
D7
WuInt
RxFilter
DoInv
RST
D6
DoFaultInt
—
DoAv
WuIntEn
R1/R0 = Register address.
— = Register not used.
D5
DiLvl
C/Q_N/P
DoN/P
DoFault
D4
QLvl
C/Q_PP
DoPP
C/QFault
D3
C/QFaultInt
C/QDEn
DoEn
UV24
D2
UV33Int
Q
DoBit
OTemp
D1
UV24Int
RxDis
LiDis
UV33En
D0
OTempInt
—
—
LDO33Dis
Status Register [R1, R0] = [0,0]
Bit
D7
D6
D5
D4
Bit Name
WuInt DoFaultInt DiLvl
QLvl
Read/Write
R
R
R
R
POR State
0
0
X
X
Reset Upon Read
Yes
Yes
No
No
Parallel Pin Configuration
(SPI is Low)
X
X
X
X
X = Unknown. These bits are dependent on the DI logic and C/Q inputs.
D3
C/QFaultInt
R
0
Yes
X
D2
UV33Int
R
0
Yes
X
D1
UV24Int
R
0
Yes
X
D0
OTempInt
R
0
Yes
X
The Status register reflects the logic levels of C/Q and DI and shows the source of interrupts that cause an IRQ/CQOC hardware
interrupt. The IRQ/CQOC interrupt is asserted when an alarm condition (OTemp, UV33Int, UV24, C/QFault, DoFault, WuInt) is
detected. All bits in the Status register are read-only. The interrupt bits return to the default state after the Status register is read. If
a C/Q or DO fault condition persists, the associated interrupt bits are immediately set after the Status register is read.
BIT
NAME
DESCRIPTION
Wake-Up Interrupt Request. WuInt is set when an IO-Link wake-up request pulse is
D7
Wulnt
detected on C/Q and the WuIntEn bit in the Mode register is set. IRQ/CQOC asserts when
WuInt is set to 1. Read the Status register to clear the WuInt bit and deassert IRQ/CQOC.
DO Fault Interrupt. DoFaultInt interrupt bit and DoFault bit (in the Mode register) are
set when a fault condition occurs on the DO driver output. The device registers a fault
D6
DoFaultInt
condition when a short-circuit or voltage fault is detected on DO (see the DO Fault
Detection section for more information). IRQ/CQOC asserts when DoFaultInt is 1. Read
the Status register to clear the DoFaultInt bit and deassert IRQ/CQOC.
DI Logic Level. The DiLvl bit mirrors the current logic level at the DI input. It is the inverse
D5
DiLvl
of the LI output and is always active regardless of the state of the LiDis bit (Table 2). DiLvl
does not affect IRQ/CQOC. DiLvl is not changed when the Status register is read.
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