MAX14826 Datasheet, PDF (27/32 Pages) Maxim Integrated Products – IO-Link Device Transceiver

MAX14826
IO-Link Device Transceiver
Mode Register [R1, R0] = [1,1]
Bit
Bit Name
Read/Write
POR State
Parallel Pin
Configuration
(SPI/PAR is low)
D7
RST
R/W
0
0
D6
WuIntEn
R/W
0
0
D5
DoFault
R
0
DOOC asserts
when DoFault
is set
D4
C/QFault
R
0
CQOC asserts
when C/QFault
is set
D3
UV24
R
0
UV asserts
when UV24
is set
D2
OTemp
R
0
0
D1
UV33En
R
0
D0
LDO33Dis
R/W
0
0
0
X = Unknown.
Use the Mode register to reset the MAX14826 and manage the 3.3V LDO. The Mode register has bits that represent
the current status of fault conditions. When writing to the Mode register, the contents of the fault indication bits
(bits 2 to 5) do not change.
BIT
NAME
DESCRIPTION
Register Reset. Set RST to 1 to reset all registers to their default power-up state. Then
set RST to 0 for normal operation.
D7
RST
The Status register is cleared and IRQ/CQOC deasserts (if asserted) when RST = 1.
Interrupts are not generated while RST = 1.
Wake-Up Interrupt Enable. Set WuIntEn to 1 to enable wake-up interrupt generation.
When WuIntEn is set, the WuInt bit in the Status register is set and IRQ/CQOC asserts
D6
WuIntEn
when a valid wake-up condition is detected. The C/Q driver must be enabled for wake-up
detection. The state of WuIntEn does not affect the WU/THSD output.
See the Wake-Up Detection section for more information.
DO Fault Status. The DoFault bit is set when a short circuit or voltage fault occurs at the
D5
DoFault
DO driver output (see the DO Fault Detection section for more information). The DoFault
and DoFaultInt bits are both set when a fault occurs on DO. DoFault is cleared when the
fault is removed.
C/Q Fault Status. The C/QFault bit is set when a short circuit or voltage fault occurs at
D4
C/QFault
the C/Q driver output (see the C/Q Fault Detection section for more information). The C/
QFault and C/QFaultInt bits are both set when a fault occurs on C/Q. C/QFault is cleared
when the fault is removed.
V_CC Undervoltage Condition. Both the UV24 and the UV24Int bits are set when V_CC
D3
UV24
falls below V_CCUVLO. UV24 is cleared when V_CC rises above the V_CC threshold. V₅
must be present for SPI V_CC undervoltage monitoring.
Temperature Warning. The OTemp bit is set when a high-temperature condition occurs
D2
OTemp
on the devices. Both the OTempInt interrupt in the Status register and the OTemp bit are
set when the junction temperature of the die rises to above +127°C (typ). The OTemp bit
is cleared when the junction temperature falls below +104°C (typ).
LDO33 UV Enable. Set the UV33En bit to 1 to assert the UV output when LDO33
D1
UV33En
voltage falls below the 2.4V (typ) undervoltage lockout threshold. The UV33En bit does
not affect the UV33Int bit in the Status register; IRQ/CQOC asserts when V_LDO33 falls
below V_LDO33UVLO regardless of the state of UV33En.
D0
LDO33Dis
LDO33 Enable/Disable. Set LDO33Dis to 1 to disable the 3.3V linear regulator (LDO33).
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