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LTC3861-1 Datasheet, PDF (9/36 Pages) Linear Technology – Dual, Multiphase Step-Down Voltage Mode DC/DC Controller with Accurate Current Sharing
LTC3861-1
Pin Functions
VCC (Pin 1): Chip Supply Voltage. Bypass this pin to GND
with a capacitor (0.1µF to 1µF ceramic) in close proximity
to the chip.
FB1 (Pin 2), FB2 (Pin 8): Error Amplifier Inverting Input.
FB1 or FB2 can be connected to VSNSOUT via a resistor
divider for remote VOUT sensing. The bottom of the divider
should be connected to the SGND pin of the IC. The other
FB, when used, is typically connected to the second VOUT
via a resistor divider, also terminated at the IC SGND pin.
COMP1 (Pin 3), COMP2 (Pin 7): Error Amplifier Outputs.
PWM duty cycle increases with this control voltage. The
error amplifiers in the LTC3861-1 are true operational
amplifiers with low output impedance. As a result, the
outputs of two active error amplifiers cannot be directly
connected together! For multiphase operation, connecting
the FB pin on an error amplifier to VCC will three-state the
output of that amplifier. Multiphase operation can then be
achieved by connecting all of the COMP pins together and
using one channel as the master and all others as slaves.
When the RUN pin is low, the respective COMP pin is
actively pulled down to ground.
VSNSOUT (Pin 4): Differential Amplifier Output. Connect
to FB1 or FB2 with a resistive divider and compensation
network for remote VOUT sensing.
VSNSN (Pin 5): Differential Sense Amplifier Inverting Input.
Connect this pin to sense ground at the output load.
VSNSP (Pin 6): Differential Sense Amplifier Noninverting
Input. Connect this pin to VOUT at the output load.
FREQ (Pin 10): Frequency Set/Select Pin. This pin sources
20µA current. If CLKIN is high or floating, then a resistor
between this pin and SGND sets the switching frequency. If
CLKIN is low, the logic state of this pin selects an internal
600kHz or 1MHz preset frequency.
CLKIN (Pin 11): External Clock Synchronization Input.
Applying an external clock between 250kHz to 2.25MHz
will cause the switching frequency to synchronize to the
clock. CLKIN is pulled high to VCC by a 50k internal resis-
tor. The rising edge of the CLKIN input waveform will align
with the rising edge of PWM1 in closed-loop operation. If
CLKIN is high or floating, a resistor from the FREQ pin to
SGND sets the switching frequency. If CLKIN is low, the
FREQ pin logic state selects an internal 600kHz or 1MHz
preset frequency.
CLKOUT (Pin 12): Digital Output Used for Daisychain-
ing Multiple LTC3861-1 ICs in Multiphase Systems. The
PHSMD pin voltage controls the relationship between
CH1 and CH2 as well as between CH1 and CLKOUT. When
both RUN pins are driven low, the CLKOUT pin is actively
pulled up to VCC.
PHSMD (Pin 13): Phase Mode Pin. The PHSMD pin volt-
age programs the phase relationship between CH1 and
CH2 rising PWM signals, as well as the phase relationship
between CH1 PWM signal and CLKOUT. Floating this pin
or connecting it to either VCC or SGND changes the phase
relationship between CH1, CH2 and CLKOUT.
ISNS1N (Pin 21), ISNS2N (Pin 20): Current Sense Am-
plifier (–) Input. The (–) input to the current amplifier is
normally connected to the respective VOUT at the inductor.
ISNS1P (Pin 22), ISNS2P (Pin 19): Current Sense Ampli-
fier (+) Input. The (+) input to the current sense amplifier
is normally connected to the midpoint of the inductor’s
parallel RC sense circuit or to the node between the induc-
tor and sense resistor if using a discrete sense resistor.
ILIM1 (Pin 23), ILIM2 (Pin 18): Current Comparator Sense
Voltage Limit Selection Pin. Connect a resistor from this
pin to SGND. This pin sources 20µA. The resultant voltage
sets the threshold for overcurrent protection.
RUN1 (Pin 24), RUN2 (Pin 17): Run Control Inputs. A
voltage above 2.25V on either pin turns on the IC. How-
ever, forcing either of these pins below 2V causes the
IC to shut down that particular channel. There are 1.5µA
pull-up currents for these pins.
PWM1 (Pin 25), PWM2 (Pin 16): (Top) Gate Signal Out-
put. This signal goes to the PWM or top gate input of the
external gate driver or integrated driver MOSFET. This is
a three-state compatible output.
PWMEN1 (Pin 26), PWMEN2 (Pin 15): Enable Pin for
Non-Three-State compatible drivers. This pin has an in-
ternal open-drain pull-up to VCC. An external resistor to
SGND is required. This pin is low when the corresponding
PWM pin is high impedance.
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