LTC3861-1 Datasheet, PDF (17/36 Pages) Linear Technology – Dual, Multiphase Step-Down Voltage Mode DC/DC Controller with Accurate Current Sharing

LTC3861-1
Applications Information
Setting the Output Voltage
The LTC3861-1 regulates the FB pins to 0.6V. FB is con-
nected to V_OUT or V_SNSOUT (for remote output sensing)
via an external resistive divider as shown in Figure 3. The
divider sets the output voltage according to the following
equation:
V_OUT = 0.6V •
1 + ^RB
R_A
Care should be taken to place the output divider resistors
and the compensation components as close as possible
to the FB pin to minimize switching noise coupling into
the control signal path.
COMP
LTC3861-1
V_OUT
FB
R_B
R_A
C_OUT
SGND
DIVIDER AND COMPENSATION COMPONENTS
PLACED NEAR FB, SGND AND COMP PINS
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Figure 3. Output Divider and Compensation Component Placement
Sensing the Output Voltage with a Differential Amplifier
When using the remote sense differential amplifier, care
should be taken to route the V_SNSP and V_SNSN PCB traces
parallel to each other all the way to the terminals of the
output capacitor or remote sensing points on the board.
In addition, avoid routing these sensitive traces near any
high speed switching nodes in the circuit. Ideally, they
should be shielded by a low impedance ground plane to
maintain signal integrity.
When using a single LTC3861-1 to regulate two output
voltages, the negative terminal of V_OUT2 should be
kelvin-connected to SGND and the differential amplifier
should be used to remotely sense V_OUT1. This will maxi-
mize output voltage accuracy for both channels.
Programming the Operating Frequency
The LTC3861-1 can be hard wired to one of two fixed fre-
quencies, linearly programmed to any frequency between
250kHz and 2.25MHz or synchronized to an external clock.
Table 1 in the Operation section shows how to connect the
CLKIN and FREQ pins to choose the mode of frequency
programming. The frequency of operation is given by the
following equation:
Frequency = (R_FREQ – 17kΩ) • 29Hz/Ω
Figure 4 shows operating frequency vs R_FREQ.
2.5
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
0.3
0.1
0
20 40 60 80 100 120
R_FREQ (kΩ)
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Figure 4. Oscillator Frequency vs R_FREQ
Frequency Synchronization
The LTC3861-1 incorporates an internal phase-locked
loop (PLL) which enables synchronization of the internal
oscillator (rising edge of PWM1) to an external clock from
250kHz to 2.25MHz.
Since the entire PLL is internal to the LTC3861-1, simply
applying a CMOS level clock signal to the CLKIN pin will
enable frequency synchronization. A resistor from FREQ
to GND is still required to set the free running frequency
close to the sync input frequency.
Choosing the Inductor and Setting the Current Limit
The inductor value is related to the switching frequency,
which is chosen based on the trade-offs discussed in the
Operation section. The inductor can be sized using the
following equation:
L
=
⎛
⎝⎜
V_OUT ⎞
f • ΔI_L ⎠⎟
•
⎛⎝⎜_1−
V_OUT ⎞
V_IN ⎠⎟
Choosing a larger value of ΔI_L leads to smaller L, but re-
sults in greater core loss (and higher output voltage ripple
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