LTC3861-1 Datasheet, PDF (12/36 Pages) Linear Technology – Dual, Multiphase Step-Down Voltage Mode DC/DC Controller with Accurate Current Sharing

LTC3861-1
Operation (Refer to Functional Diagram)
Main Control Architecture
The LTC3861-1 is a dual-channel/dual-phase, constant-
frequency, voltage mode controller for DC/DC step-down
applications. It is designed to be used in a synchronous
switching architecture with external integrated-driver MOS-
FETs or power blocks, or external drivers and N-channel
MOSFETs using single wire three-state PWM interfaces.
The controller allows the use of sense resistors or lossless
inductor DCR current sensing to maintain current balance
between phases and to provide overcurrent protection.
The operating frequency is selectable from 250kHz to
2.25MHz. To multiply the effective switching frequency,
multiphase operation can be extended to 3, 4, 6, or 12
phases by paralleling up to six controllers. In single or
3-phase operation, the 2nd or 4th channel can be used
as an independent output.
The output of the differential amplifier is connected to
the error amplifier inverting input (FB) through a resistor
divider. The remote sense differential amplifier output
(V_SNSOUT) provides a signal equal to the differential voltage
(V_SNSP – V_SNSN) sensed across the output capacitor, but
re-referenced to the local ground (SGND). This permits
accurate voltage sensing at the load, without regard to the
potential difference between its ground and local ground.
In the main voltage mode control loop, the error ampli-
fier output (COMP) directly controls the converter duty
cycle in order to drive the FB pin to 0.6V in steady state.
Dynamic changes in output load current can perturb the
output voltage. When the output is below regulation,
COMP rises, increasing the duty cycle. If the output rises
above regulation, COMP will decrease, decreasing the
duty cycle. As the output approaches regulation, COMP
will settle to the steady-state value representing the step-
down conversion ratio.
In normal operation, the PWM latch is set high at the begin-
ning of the clock cycle (assuming COMP > 0.5V). When
the (line feedforward compensated) PWM ramp exceeds
the COMP voltage, the comparator trips and resets the
PWM latch. If COMP is less than 0.5V at the beginning
of the clock cycle, as in the case of an overvoltage at the
outputs, the PWM pin remains low throughout the entire
cycle. When the PWM pin goes high it has a minimum
on-time of approximately 20ns and a minimum off-time
of approximately one-twelth the switching period.
Current Sharing
In multiphase operation, the LTC3861-1 also incorporates
an auxiliary current sharing loop. Inductor current is
sampled each cycle. The master’s current sense amplifier
output is averaged at the I_AVG pin. A small capacitor con-
nected from I_AVG to GND (typically 100pF) stores a voltage
corresponding to the instantaneous average current of the
master. Each phase integrates the difference between its
current and the master’s. Within each phase the integrator
output is proportionally summed with the system error
amplifier voltage (COMP), adjusting that phase’s duty
cycle to equalize the currents. When multiple ICs are
daisychained the I_AVG pins must be connected together.
When the phases are operated independently, the I_AVG
pin should be tied to ground. Figure 1 shows a transient
load step with current sharing in a 3-phase system.
I_{L1 (L= 0.47µH)}
10A/DIV
I_{L2 (L= 0.25µH)}
10A/DIV
I_{L3 (L= 0.47µH)}
10A/DIV
V_OUT
100mV/DIV
AC-COUPLED
V_IN = 12V
V_OUT = 1V
50µs/DIV
38611 F01
I_LOAD STEP = 0A TO 30A TO 0A
f_SW = 500kHz EXTERNAL CLOCK
Figure 1. Mismatched Inductor Load Step Transient Response
(3-Phase Using FDMF6707B DrMOS)
Overcurrent Protection
The current sense amplifier outputs also connect to overcur-
rent (OC) comparators that provide fault protection in the
case of an output short. When an OC fault is detected for
128 consecutive clock cycles, the controller three-states
the PWM output, resets the soft-start capacitor, and waits
for 32768 clock cycles before attempting to start up again.
The 128 consecutive clock cycle counter has a 7-cycle
hysteresis window, after which it will reset. The LTC3861-1
also provides negative OC (NOC) protection by preventing
38611f
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