LTC3861-1 Datasheet, PDF (30/36 Pages) Linear Technology – Dual, Multiphase Step-Down Voltage Mode DC/DC Controller with Accurate Current Sharing

LTC3861-1
Applications Information
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power. It is often useful
to analyze individual losses to determine what is limiting
the efficiency and which change would produce the most
improvement. Percent efficiency can be expressed as:
%Efficiency = 100% - (L1 + L2 + L3 + …)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the system produce
losses, three main sources usually account for most of
the losses in LTC3861-1 applications: 1) I²R losses, 2)
topside MOSFET transition losses, 3) gate drive current.
1. I²R losses occur mainly in the DC resistances of the
MOSFET, inductor, PCB routing, and input and output
capacitor ESR. Since each MOSFET is only on for part
of the cycle, its on-resistance is effectively multiplied
by the percentage of the cycle it is on. Therefore in high
step-down ratio applications the bottom MOSFET should
have a much lower R_DS(ON) than the top MOSFET. It
is crucial that careful attention is paid to the layout of
the power path on the PCB to minimize its resistance.
In a 2-phase, 1.2V output, 60A system, 1mΩ of PCB
resistance at the output costs 5% in efficiency.
2. Transition losses apply only to the topside MOSFET but
in 12V input applications are a very significant source
of loss. They can be minimized by choosing a driver
with very low drive resistance and choosing a MOSFET
with low Q_G, R_G and C_RSS.
3. Gate drive current is equal to the sum of the top and
bottom MOSFET gate charges multiplied by the fre-
quency of operation. However, many drivers employ a
linear regulator to reduce the input voltage to a lower
gate drive voltage. This multiplies the gate loss by that
step down ratio. In high frequency applications it may
be worth using a secondary user supplied rail for gate
drive to avoid the linear regulator.
Other sources of loss include body or Schottky diode
conduction during the driver dependent non-overlap time
and inductor core losses.
30
Design Example
As a design example, consider a 2-phase application
where V_IN = 12V, V_OUT = 1.2V, I_LOAD = 60A and f_SWITCH =
300kHz. Assume that a secondary 5V supply is available
for the LTC3861-1 V_CC supply.
The inductance value is chosen based on a 25% ripple
assumption. Each channel supplies an average 30A to the
load resulting in 7.7A peak-peak ripple:
ΔI_L
=
V_OUT
•
⎛⎝⎜_1–
f •L
V_OUT ⎞
V_IN ⎠⎟
A 470nH inductor per phase will create 7.7A peak-to-
peak ripple. A 0.47µH inductor with a DCR of 0.67mΩ
typical is selected from the WÜRTH 744355147 series.
Float CLKIN and connect 28kΩ from FREQ to SGND for
300kHz operation. Setting I_LIMIT = 54A per phase leaves
plenty of headroom for transient conditions while still
adequately protecting against inductor saturation. This
corresponds to:
R_ILIM
=
18.5
•
54A
• 0.67mΩ
20µA
+
0.53V
=
58.5kΩ
Choose 59kΩ.
For the DCR sense filter network, we can choose R = 2.87k
and C = 220nF to match the L/DCR time constant of the
inductor.
A loop crossover frequency of 45kHz provides good tran-
sient performance while still being well below the switching
frequency of the converter. Six 330µF 9mΩ POSCAPs and
four 100µF ceramic capacitors are chosen for the output
capacitors to maintain supply regulation during severe
transient conditions and to minimize output voltage ripple.
The following compensation values (Figure 13) were
determined empirically:
R1 = 10k
R2 = 5.9k
R3 = 280Ω
C1 = 4.7nF
C2 = 100pF
C3 = 3.3nF
38611f