LTC3861-1 Datasheet, PDF (16/36 Pages) Linear Technology – Dual, Multiphase Step-Down Voltage Mode DC/DC Controller with Accurate Current Sharing

LTC3861-1
Operation (Refer to Functional Diagram)
would be with a single comparable output stage, where n
is equal to the number of phases.
The main advantages of PolyPhase operation are ripple
current cancellation in the input and output capacitors, a
faster load step response due to a smaller clock delay and
reduced thermal stress on the inductors and MOSFETs
due to current sharing between phases. These advantages
allow for the use of a smaller size or a smaller number
of components.
Power Good Indicator Pins (PGOOD1, PGOOD2)
Each PGOOD pin is connected to the open drain of an
internal pull-down device which pulls the PGOOD pin
low when the corresponding FB pin voltage is outside
the PGOOD regulation window (±7.5% entering regula-
tion, ±10% leaving regulation). The PGOOD pins are also
pulled low when the corresponding RUN pin is low, or
during UVLO.
When the FB pin voltage is within the ±10% regulation
window, the internal PGOOD MOSFET is turned off and the
pin is normally pulled up by an external resistor. When the
FB pin is exiting a fault condition (such as during normal
output voltage start-up, prior to regulation), the PGOOD
pin will remain low for an additional 30μs. This allows
the output voltage to reach steady-state regulation and
prevents the enabling of a heavy load from retriggering
a UVLO condition.
In multiphase applications, one FB pin and error amplifier
are used to control all of the phases. Since the FB pins
for the unused error amplifiers are connected to V_CC (in
order to three-state these amplifiers), the PGOOD outputs
for these amplifiers will be asserted. In order to prevent
falsely reporting a fault condition, the PGOOD outputs
for the unused error amplifiers should be left open. Only
the PGOOD output for the master control error amplifier
should be connected to the fault monitor.
PWM and PWMEN Pins
The PWM pins are three-state compatible outputs, de-
signed to drive MOSFET drivers, DrMOSs, power blocks,
etc., which do not represent a heavy capacitive load. An
external resistor divider may be used to set the voltage to
mid-rail while in the high impedance state.
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The PWMEN outputs have an open-drain pull-up to V_CC and
require an appropriate external pull-down resistor. This pin
is intended to drive the enable pins of the MOSFET driv-
ers that do not have three-state compatible PWM inputs.
PWMEN is low only when PWM is high impedance, and
high at any other PWM state.
Line Feedforward Gain
In a typical LTC3861-1 circuit, the feedback loop consists
of the line feedforward circuit, the modulator, the external
inductor, the output capacitor and the feedback amplifier
with its compensation network. All these components
affect loop behavior and need to be accounted for in the
loop compensation. The modulator consists of the PWM
generator, the external output MOSFET drivers and the
external MOSFETs themselves. The modulator gain varies
linearly with the input voltage. The line feedforward circuit
compensates for this change in gain, and provides a con-
stant gain from the error amplifier output to the inductor
input regardless of input voltage. From a feedback loop
point of view, the combination of the line feedforward
circuit and the modulator looks like a linear voltage transfer
function from COMP to the inductor input and has a gain
roughly equal to 12V/V.
The LTC3861-1 has a wide V_IN and switching frequency
range. The CONFIG pin is used to select the optimum
range of operation for the internal multiplier, in order to
maintain a constant line feedforward gain across a wide
V_IN and switching frequency range. The CONFIG is a three-
state pin and can be connected to SGND, V_CC, or floated.
Floating the pin externally is a valid selection as there are
internal steering resistors. The selection range based on
V_IN and switching frequency is summarized in Table 3.
Table 3. Line Feedforward Range Selection
CONFIG PIN
GND (or) FLOAT
V_CC
V_IN
< 14V
> 14V
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