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LTC3718_15 Datasheet, PDF (7/20 Pages) Linear Technology – Low Input Voltage DC/DC Controller for DDR/QDR Memory Termination
LTC3718
PI FU CTIO S
RUN/SS (Pin 1): Run Control and Soft-Start Input. A
capacitor to ground at this pin sets the ramp time to full
output current (approximately 3s/µF) and the time delay
for overcurrent latchoff (see Applications Information).
Forcing this pin below 0.8V shuts down the device.
VON (Pin 2): On-Time Voltage Input. Voltage trip point for
the on-time comparator. Tying this pin to the output
voltage makes the on-time proportional to VOUT. The
comparator input defaults to 0.7V when the pin is grounded,
2.4V when the pin is tied to INTVCC.
PGOOD (Pin 3): Power Good Output. Open-drain logic
output that is pulled to ground when the output voltage of
the buck section is not within ±10% of the regulation point.
VRNG (Pin 4): Sense Voltage Range Input. The voltage at
this pin is ten times the nominal sense voltage at maxi-
mum output current and can be set from 0.5V to 2V by a
resistive divider from INTVCC. The nominal sense voltage
defaults to 70mV when this pin is tied to ground, 140mV
when tied to INTVCC.
ITH (Pin 5): Current Control Threshold and Error Amplifier
Compensation Point. The current comparator threshold
increases with this control voltage. The voltage ranges
from 0V to 2.4V with 1.2V corresponding to zero sense
voltage (zero current).
SGND (Pins 6, 11): Signal Ground. All small-signal com-
ponents and compensation components should connect to
this ground, which in turn connects to PGND at one point.
ION (Pin 7): On-Time Current Input. Tie a resistor from VIN
to this pin to set the one-shot timer current and thereby set
the switching frequency.
VFB1 (Pin 8): Error Amplifier Feedback Input. This pin
connects the negative error amplifier input to VOUT.
VREF (Pin 9): Positive Input of Internal Error Amplifier.
Reference voltage for output voltage, power good thresh-
old, and short-circuit shutdown threshold. The output
voltage is set to VREF/2.
SHDN (Pin 10): Shutdown, Active Low. Tie to 1V or more
to enable boost converter portion of the LTC3718. Ground
to shut down.
VFB2 (Pin 12): Boost Converter Feedback. The VFB2 pin is
connected to INTVCC through a resistor divider to set the
voltage on INTVCC. Set INTVCC voltage according to:
VINTVCC = 1.23V(1 + RF2/RF1)
SW2 (Pin 13): Boost Converter Switch Pin. Connect
inductor/diode for boost converter portion here. Minimize
trace area at this pin to keep EMI down.
PGND (Pins 14, 19): Power Ground. Connect these pins
closely to the source of the bottom N-channel MOSFET,
the (–) terminal of CVCC and the (–) terminal of CIN.
VIN2 (Pin 15): Input Supply Pin for Boost Converter
Portion of LTC3718. Must be locally bypassed.
VIN1 (Pin 16): Main Input Supply. Decouple this pin to
PGND with at least a 1µF ceramic capacitor.
INTVCC (Pin 17): Internal Regulator Output. The driver and
control circuits are powered from this voltage when VIN is
greater than 5V. Decouple this pin to power ground with a
minimum of 4.7µF low ESR tantalum or ceramic capacitor.
BG (Pin 18): Bottom Gate Drive. Drives the gate of the
bottom N-channel MOSFET between ground and INTVCC.
SENSE– (Pin 20): Negative Current Sense Comparator
Input. The (–) input to the current comparator is normally
connected to power ground unless using a resistive di-
vider from INTVCC (see Applications Information).
SENSE+ (Pin 21): Positive Current Sense Comparator
Input. The (+) input to the current comparator is normally
connected to the SW node unless using a sense resistor
(see Applications Information).
SW1 (Pin 22): Switch Node. The (–) terminal of the
bootstrap capacitor CB connects here. This pin swings
from a diode voltage drop below ground up to VIN.
TG (Pin 23): Top Gate Drive. Drives the top N-channel
MOSFET with a voltage swing equal to INTVCC superim-
posed on the switch node voltage SW.
BOOST (Pin 24): Boosted Floating Driver Supply. The (+)
terminal of the bootstrap capacitor CB connects here. This
pin swings from a diode voltage drop below INTVCC up to
VIN + INTVCC.
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