LTC3718_15 Datasheet, PDF (13/20 Pages) Linear Technology – Low Input Voltage DC/DC Controller for DDR/QDR Memory Termination

LTC3718
APPLICATIO S I FOR ATIO
transients. The output ripple ∆V_OUT is approximately
bounded by:
∆V_OUT
≤

∆I_{L}ESR +
1
8fC _OUT


Since ∆I_L increases with input voltage, the output ripple is
highest at maximum input voltage. Typically, once the ESR
requirement is satisfied, the capacitance is adequate for
filtering and has the necessary RMS current rating.
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, aluminum electrolytic and
ceramic capacitors are all available in surface mount
packages. Special polymer capacitors offer very low ESR
but have lower capacitance density than other types.
Tantalum capacitors have the highest capacitance density
but it is important to only use types that have been surge
tested for use in switching power supplies. Aluminum
electrolytic capacitors have significantly higher ESR, but
can be used in cost-sensitive applications providing that
consideration is given to ripple current ratings and long
term reliability. Ceramic capacitors have excellent low
ESR characteristics but can have a high voltage coeffi-
cient and audible piezoelectric effects. The high Q of
ceramic capacitors with trace inductance can also lead to
significant ringing. When used as input capacitors, care
must be taken to ensure that ringing from inrush currents
and switching does not pose an overvoltage hazard to the
power switches and controller. To dampen input voltage
transients, add a small 5µF to 50µF aluminum electrolytic
capacitor with an ESR in the range of 0.5Ω to 2Ω. High
performance through-hole capacitors may also be used,
but an additional ceramic capacitor in parallel is recom-
mended to reduce the effect of their lead inductance.
Top MOSFET Driver Supply (C_B, D_B)
An external bootstrap capacitor C_B connected to the BOOST
pin supplies the gate drive voltage for the topside MOSFET.
This capacitor is charged through diode D_B from INTV_CC
when the switch node is low. When the top MOSFET turns
on, the switch node rises to V_IN and the BOOST pin rises
to approximately V_IN + INTV_CC. The boost capacitor needs
to store about 100 times the gate charge required by the
top MOSFET. In most applications a 0.1µF to 0.47µF X5R
or X7R dielectric capacitor is adequate.
Fault Condition: Current Limit
The maximum inductor current is inherently limited in a
current mode controller by the maximum sense voltage. In
the LTC3718, the maximum sense voltage is controlled by
the voltage on the V_RNG pin. With valley current control,
the maximum sense voltage and the sense resistance
determine the maximum allowed inductor valley current.
The corresponding output current limit is:
I_{LIMITPOSITIVE}
=
V_SNS(MAX)
R_DS(ON)ρ_T
+
1
2
∆I_L
I_{LIMITNEGATIVE}
=
V_SNS(MIN)
R_DS(ON)ρ_T
−
1
2
∆I_L
The current limit value should be checked to ensure that
I_LIMIT(MIN) > I_OUT(MAX). The minimum value of current limit
generally occurs with the largest V_IN at the highest ambi-
ent temperature, conditions that cause the largest power
loss in the converter. Note that it is important to check for
self-consistency between the assumed MOSFET junction
temperature and the resulting value of I_LIMIT which heats
the MOSFET switches.
Caution should be used when setting the current limit
based upon the R_DS(ON) of the MOSFETs. The maximum
current limit is determined by the minimum MOSFET on-
resistance. Data sheets typically specify nominal and
maximum values for R_DS(ON), but not a minimum. A
reasonable assumption is that the minimum R_DS(ON) lies
the same amount below the typical value as the maximum
lies above it. Consult the MOSFET manufacturer for further
guidelines.
Minimum Off-time and Dropout Operation
The minimum off-time t_OFF(MIN) is the smallest amount of
time that the LTC3718 is capable of turning on the bottom
MOSFET, tripping the current comparator and turning the
MOSFET back off. This time is generally about 250ns. The
minimum off-time limit imposes a maximum duty cycle of
t_ON/(t_ON + t_OFF(MIN)). If the maximum duty cycle is reached,
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