LTC3718_15 Datasheet, PDF (18/20 Pages) Linear Technology – Low Input Voltage DC/DC Controller for DDR/QDR Memory Termination

LTC3718
APPLICATIO S I FOR ATIO
PC Board Layout Checklist
When laying out a PC board follow one of the two
suggested approaches. The simple PC board layout
requires a dedicated ground plane layer. Also, for higher
currents, it is recommended to use a multilayer board to
help with heat sinking power components.
• The ground plane layer should not have any traces and
it should be as close as possible to the layer with power
MOSFETs.
• Place C_IN, C_OUT, MOSFETs, D1 and inductor all in one
compact area. It may help to have some components
on the bottom side of the board.
• Place LTC3718 chip with Pins 13 to 24 facing the
power components. Keep the components connected
to Pins 1 to 12 close to LTC3718 (noise sensitive
components).
• Use an immediate via to connect the components to
ground plane including SGND and PGND of LTC3718.
Use several bigger vias for power components.
• Use compact plane for switch node (SW) to improve
cooling of the MOSFETs and to keep EMI down.
• Use planes for V_IN and V_OUT to maintain good voltage
filtering and to keep power losses low.
• Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise
of power component. You can connect the copper
areas to any DC net (V_IN, V_OUT, GND or to any other DC
rail in your system).
When laying out a printed circuit board, without a ground
plane, use the following checklist to ensure proper opera-
tion of the controller. These items are also illustrated in
Figure 8.
• Segregate the signal and power grounds. All small
signal components should return to the SGND pin at
one point which is then tied to the PGND pin close to
the source of M2.
• Place M2 as close to the controller as possible, keep-
ing the PGND, BG and SW traces short.
• Connect the input capacitor(s) C_IN close to the power
MOSFETs. This capacitor carries the MOSFET AC
current.
• Keep the high dV/dt SW, BOOST and TG nodes away
from sensitive small-signal nodes.
• Connect the INTV_CC decoupling capacitor C_VCC closely
to the INTV_CC and PGND pins.
• Connect the top driver boost capacitor C_B closely to
the BOOST and SW pins.
18
C1 _RC
R_ON
R_F3
C_SS
1
RUN/SS
2
V_ON
3
PGOOD
24
BOOST
23
TG
22
SW1
C_B
D_B
4
V_RNG
SENSE^{+ 21}
5
I_TH
SENSE^{– 20}
6
19
SGND1 PGND1
C2
7
LTC3718
18
I_ON
BG
8
V_FB1
17
INTV_CC
C_VCC
9
V_REF
16
V_IN1
10
SHDN
15
V_IN2
11
14
C_IN2
SGND2 PGND2
L2
12
V_FB2
D3
13
SW2
R_F5
R_F4
M1
L1
M2
D2
V_IN
+
C_IN
V_OUT
C_OUT
–
3718 F08
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 8. LTC3718 Layout Diagram
3718fa