LTC3718_15 Datasheet, PDF (1/20 Pages) Linear Technology – Low Input Voltage DC/DC Controller for DDR/QDR Memory Termination

LTC3718
Low Input Voltage
DC/DC Controller for
DDR/QDR Memory Termination
FEATURES
s _{Very Low VIN(MIN): 1.5V}
s _{Ultrafast Transient Response}
s _{True Current Mode Control}
s _{5V Drive for N-Channel MOSFETs Eliminates}
Auxillary 5V Supply
s _{No Sense Resistor Required}
s _{Uses Standard 5V Logic-Level N-Channel MOSFETs}
s _{VOUT(MIN): 0.4V}
s _{VOUT Tracks 1/2 VIN or External VREF}
s _{Symmetrical Source and Sink Output Current Limit}
s _{Adjustable Switching Frequency}
s _{tON(MIN) <100ns}
s _{Power Good Output Voltage Monitor}
s _{Programmable Soft-Start}
s _{Output Overvoltage Protection}
s _{Optional Short-Circuit Shutdown Timer}
s _{Small 24-Lead SSOP Package}
U
APPLICATIO S
s _{Bus Termination: DDR/QDR Memory, SSTL, HSTL, ...}
s _{Servers, RAID Systems}
s _{Distributed Power Systems}
s _{Synchronous Buck with General Purpose Boost}
DESCRIPTIO
The LTC^®3718 is a high current, high efficiency synchro-
nous switching regulator controller for DDR and QDR^TM
memory termination. It operates from an input as low as
1.5V and provides a regulated output voltage equal to
(0.5)V_IN. The controller uses a valley current control
architecture to enable high frequency operation with very
low on-times without requiring a sense resistor. Operating
frequency is selected by an external resistor and is com-
pensated for variations in V_IN and V_OUT. The LTC3718 uses
a pair of standard 5V logic level N-channel external
MOSFETs, eliminating the need for expensive P-channel
or low threshold devices.
Forced continuous operation reduces noise and RF inter-
ference. Fault protection is provided by internal foldback
current limiting, an output overvoltage comparator and an
optional short-circuit timer. Soft-start capability for sup-
ply sequencing can be accomplished using an external
timing capacitor. OPTI-LOOP^® compensation allows the
transient response to be optimized over a wide range of
loads and output capacitors.
, LTC and LT are registered trademarks of Linear Technology Corporation.
OPTI-LOOP is a registered trademark of Linear Technology Corporation. No R_SENSE is a
trademark of Linear Technology Corporation. QDR RAMs and Quad Data Rate RAMs comprise a
new family of products developed by Cypress Semiconductor, IDT and Micron Technology, Inc.
TYPICAL APPLICATIO
R_ON
237k
V_OUT
C_SS
0.1µF
C1 820pF X7R _{RC 4.75k}
R_F1 12.1k
SHDN
BOOST
V_REF
TG
LTC3718
I_ON
SW1
V_FB1
SENSE⁺
PGOOD PGND1
SENSE^–
RUN/SS
I_TH
SGND1
BG
INTV_CC
V_IN1
V_IN2
SGND2 PGND2
V_FB2
SW2
R_F2 37.4k
D_B
CMDSH-3
V_IN
C_IN1
2.5V
22µF
×2
C_B
0.33µF
M1
Si7440DP
D1
B340A
L1 0.8µH
M2
Si7440DP
+
D2
B340A
C_OUT
470µF
×2
V_OUT
1.25V
±10A
C_IN2
V_IN
4.7µF L2
4.7µH
C_VCC1
10µF
D3
MBR0520
C_OUT: SANYO POSCAP 4TPB470M
L1: SUMIDA CEP125-0R8MC
L2: PANASONIC ELJPC4R7MF
3718 TA01
Figure 1. High Efficiency Bus Termination Supply without Auxiliary 5V Supply
Efficiency vs Load Current
100
90
V_IN = 2.5V
V_OUT = 1.25V
80
70
60
50
40
30
20
10
0
0.01
FIGURE 1 CIRCUIT
0.1
1
10
100
LOAD CURRENT (A)
3718 G05/TA01a
3718fa
1