LTC3300-1 Datasheet, PDF(39/44 Page) Linear Technology – High Effciency Bidirectional Multicell Battery Balancer

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LTC3300-1 Datasheet, PDF (39/44 Pages) Linear Technology – High Effciency Bidirectional Multicell Battery Balancer

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LTC3300-1

APPLICATIONS INFORMATION

PCB Layout Considerations

The LTC3300-1 is capable of operation with as much as

40V between BOOST+ and Vâ. Care should be taken on

the PCB layout to maintain physical separation of traces

at different potentials. The pinout of the LTC3300-1 was

chosen to facilitate this physical separation. There is no

more than 8.4V between any two adjacent pins with the

exception of two instances (VMODE to CSBO, BOOST to

SDOI/BOOSTâ). In both instances, one of the pins (VMODE,

BOOST) is pin-strapped in the application to Vâ or VREG

and does not need to route far from the LTC3300-1. The

package body is used to separate the highest voltage

(e.g., 25.2V) from the lowest voltage (0V). As an example,

Figure 18 shows the DC voltage on each pin with respect

to Vâ when six 4.2V battery cells are connected to the

LTC3300-1.

0V TO 4.8V

G6SâPIN 1

I6S

G5S

I5S

G4S

I4S

G3S

I3S

G2S

I2S

G1S

I1S

LTC3300-1

(EXPOSED PAD = 0V)

C5 21V

G5P 16.8V TO 25.2V

I5P 16.8V

C4 16.8V

G4P 12.6V TO 21V

I4P 12.6V

C3 12.6V

G3P 8.4V TO 16.8V

I3P 8.4V

C2 8.4V

G2P 4.2V TO 12.6V

I2P 4.2V

33001 F18

Figure 18. Typical Pin Voltages for Six 4.2V Cells

Additional âgood practiceâ layout considerations are as

follows:

1. The VREG pin should be bypassed to the exposed pad

and to Vâ, each with 1ÂµF or larger capacitors as close

to the LTC3300-1 as possible.

2. The differential cell inputs (C6 to C5, C5 to C4, â¦, C1 to

exposed pad) should be bypassed with a 1ÂµF or larger

capacitor as close to the LTC3300-1 as possible. This

is in addition to bulk capacitance present in the power

stages.

3. Pin 21 (Vâ) is the ground sense for current sense resis-

tors connected to I1S-I6S and I1P (seven resistors).

Pin 21 should be Kelvined as well as possible with low

impedance traces to the ground side of these resistors

before connecting to the LTC3300-1 exposed pad.

4. Cell inputs C1 to C5 are the ground sense for current

sense resistors connected to I2P-I6P (five resistors).

These pins should be Kelvined as well as possible

with low impedance traces to the ground side of these

resistors.

5. The ground side of the maximum on-time setting resis-

tors connected to the RTONS and RTONP pins should

be Kelvined to Pin 21 (Vâ) before connecting to the

LTC3300-1 exposed pad.

6. Trace lengths from the LTC3300-1 gate drive outputs

(G1S-G6S and G1P-G6P) and current sense inputs

(I1S-I6S and I1P-I6P) should be as short as possible.

7. The boosted gate drive components (diode and ca-

pacitor), if used, should form a tight loop close to the

LTC3300-1 C6, BOOST+, and BOOSTâ pins.

8. For the external power components (transformer, FETs

and current sense resistors), it is important to keep the

area encircled by the two high speed current switching

loops (primary and secondary) as tight as possible.

This is greatly aided by having two additional bypass

capacitors local to the power circuit: one differential

cell to cell and one from the transformer secondary to

local Vâ.

A representative layout incorporating all of these recom-

mendations is implemented on the DC2064A demo board

for the LTC3300-1 (with further explanation in its accom-

panying demo board manual). PCB layout files (.GRB) are

also available from the factory.

For more information www.linear.com/product/LTC3300-1

33001f

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