LTC3300-1 Datasheet, PDF (28/44 Pages) Linear Technology – High Effciency Bidirectional Multicell Battery Balancer

LTC3300-1
OPERATION
Read Balance Status
If the command bits program Read Balance Status, suc-
cessive 16-bit status data (12 bits of data plus associated
4-bit CRC) are shifted out MSB first per Table 6. Similar
to a Readback Balance Command, the last 4 bits in each
16-bit balance status are used for error detection. The
first 12 bits of the status are input to a cyclic redundancy
check (CRC) block employing the same characteristic
polynomial used for write commands. The LTC3300-1
will calculate and append the appropriate 4-bit CRC to
the outgoing 12‑bit message which can then be used for
microprocessor error checking. The sequence of outcom-
ing data during readback is:
Status data (bottom chip), Status data (2nd chip from
bottom), …, Status data (top chip)
Note that the CRC bits in the Read Balance Status are
inverted. This was done so that an “all zeros” readback
is invalid.
The first 6 bits of the read balance status indicate if there
is sufficient gate drive for each of the 6 balancers. These
bits correspond to the right-most column in Table 1, but
can only be logic high for a given balancer following an
execute command involving that same balancer. If a bal-
ancer is not active, its Gate Drive OK bit will be logic low.
The 7th, 8th, and 9th bits in the read balance status indicate
that all 6 cells are not overvoltage, that the transformer
secondary is not overvoltage, and that the LTC3300-1 die
is not overtemperature, respectively. These 3 bits can only
be logic high following an execute command involving at
least one balancer. The 10th, 11th, and 12th bits in the
read balance status are currently not used and will always
be logic zero. As an example, if balancers 1 and 4 are both
active with no voltage or temperature faults, the 12-bit
read balance status should be 100100111000.
Execute Balance Command
If the command bits program Execute Balance Command,
the last successfully written and latched in balance com-
mand will be executed immediately. All subsequent (write)
data will be ignored until CSBI transitions high and then
low again.
Pause/Resume Balancing (via SPI Port)
The LTC3300-1 provides a simple means to interrupt bal-
ancing in progress (stack wide) and then restart without
having to rewrite the previous balance command to all
LTC3300-1 ICs in the stack. To pause balancing, simply
write an 8-bit Execute Balance Command with the parity
bit flipped: 10101110. To resume balancing, simply write
an Execute Balance Command with the correct parity:
10101111. This feature is useful if precision cell voltage
measurements want to be performed during balancing
with the stack “quiet.” Immediate pausing of balancing
in progress will occur for any 8-bit Command Byte with
incorrect parity.
The restart time is typically 2ms which is the same as the
delayed start time after a new or different balance command
(t_{DLY_START}). It is measured from the 8th rising SCKI edge
until the balancer turns on and is illustrated in G27 in the
Typical Performance Characteristics section.
Table 6. Read Balance Status Data Bit Mapping (defaults to 0x000F in Reset State)
Gate Gate Gate Gate Gate Gate Cells Sec Temp 0
0
Drive 1 Drive 2 Drive 3 Drive 4 Drive 5 Drive 6 Not OV Not OV OK
OK
OK
OK
OK
OK
OK
(MSB)
0 CRC[3] CRC[2] CRC[1] CRC[0]
(LSB)
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