LTC3300-1 Datasheet, PDF (11/44 Pages) Linear Technology – High Effciency Bidirectional Multicell Battery Balancer

LTC3300-1
PIN FUNCTIONS
G1P, G2P, G3P, G4P, G5P, G6P (Pins 23, 26, 29, 32, 35,
38): G1P through G6P are gate driver outputs for driving
external NMOS transistors connected in series with the
primary windings of transformers connected in parallel
with battery cells 1 through 6.
C1, C2, C3, C4, C5, C6 (Pins 24, 27, 30, 33, 36, 39):
C1 through C6 connect to the positive terminals of bat-
tery cells 1 through 6. Connect the negative terminal of
battery cell 1 to V^–.
BOOST⁺ (Pin 40): Boost⁺ Pin. Connects to the anode of
the external flying capacitor used for generating sufficient
gate drive necessary for balancing the topmost battery cell
in a given LTC3300-1 sub-stack. A Schottky diode from C6
to BOOST⁺ is needed as well. Alternately, the BOOST⁺ pin
can connect to one cell up in the above sub-stack (if pres-
ent). This pin is effectively C7. (Note: “Sub-stack” refers
to the 3-6 battery cells connected locally to an individual
LTC3300-1 as part of a larger stack.)
BOOST^– (Pin 41): Boost^– Pin. Connects to the cathode of
the external flying capacitor used for generating sufficient
gate drive necessary for balancing the topmost battery cell
in a given LTC3300-1 sub-stack. Alternately, if the BOOST⁺
pin connects to the next higher cell in the above sub-stack
(if present), this pin is a no connect.
BOOST (Pin 42): Enable Boost Pin. Connect BOOST to V_REG
to enable the boosted gate drive needed for balancing the
top cell in a given LTC3300-1 sub-stack. If the BOOST⁺ pin
can be connected to the next cell up in the stack (i.e., C1
of the next LTC3300-1 in the stack), then BOOST should
be tied to V^– and BOOST^– no connected. This pin must
be tied to either V_REG or V^–.
SDOI (Pin 43): Serial Data Output/Input. SDOI transfers
data to and from the next IC higher in the daisy chain when
writing and reading. See Serial Port in the Applications
Information section.
SCKO (Pin 44): Serial Clock Output. SCKO is a buffered
and one-shotted version of the serial clock input, SCKI,
when CSBI is low. SCKO drives the next IC higher in the
daisy chain. See Serial Port in the Applications Informa-
tion section.
CSBO (Pin 45): Chip Select (Active Low) Output. CSBO
is a buffered version of the chip select input, CSBI. CSBO
drives the next IC higher in the daisy chain. See Serial Port
in the Applications Information section.
V_MODE (Pin 46): Voltage Mode Input. When V_MODE is tied
to V_REG, the CSBI, SCKI, SDI and SDO pins are configured
as voltage inputs and outputs. This means these pins
accept V_REG-referred rail-to-rail logic levels. Connect
V_MODE to V_REG when the LTC3300-1 is the bottom device
in a daisy chain.
When V_MODE is tied to V^–, the CSBI, SCKI and SDI pins
are configured as current inputs and outputs, and SDO is
unused. Connect V_MODE to V^– when the LTC3300-1 is be-
ing driven by another LTC3300-1 lower in the daisy chain.
This pin must be tied to either V_REG or V^­–.
TOS (Pin 47): Top Of Stack Input. Tie TOS to V_REG when
the LTC3300-1 is the top device in a daisy chain. Tie TOS
to V^– when the LTC3300-1 is any other device in the daisy
chain. When TOS is tied to V_REG, the LTC3300-1 ignores
the SDOI input. When TOS is tied to V^–, the LTC3300-1
expects data to be passed to and from the SDOI pin. This
pin must be tied to either V_REG or V^–.
V_REG (Pin 48): Linear Voltage Regulator Output. This 4.8V
output should be bypassed with a 1µF or larger capacitor
to V^–. The V_REG pin is capable of supplying up to 40mA
to internal and external loads. The V_REG pin does not sink
current.
V^– (Exposed Pad Pin 49): The exposed pad should be
connected to a continuous (ground) plane biased at V^– on
the second layer of the printed circuit board by several
vias directly under the LTC3300-1.
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