LTC3300-1 Datasheet, PDF (36/44 Pages) Linear Technology – High Effciency Bidirectional Multicell Battery Balancer

LTC3300-1
APPLICATIONS INFORMATION
Analysis of Stack Terminal Currents in Shutdown
As given in the Electrical Characteristics table, the qui-
escent current of the LTC3300-1 when not balancing is
16μA at the C6 pin and zero at the C1 through C5 pins.
All of this 16μA shows up at the V^– pin of the LTC3300-1.
In addition, the SPI port when not communicating (i.e.,
CSBI = 1) contributes an additional 2.5μA per high side
line (CSBO/SCKO/SDOI), or 7.5μA to the V^– pin current
of each LTC3300-1 in the stack which is not top of stack
(TOS = 0). This additional current does not add to the local
C6 pin current but rather to the C6 pin current of the next
higher LTC3300-1 in the stack as it is passed in through
the CSBI/SCKI/SDI pins. To the extent that the 16μA and
7.5μA currents match perfectly chip-to-chip in a long series
stack, the resultant stack terminal currents in shutdown
are as follows: 23.5μA out of the top of stack node, 7.5μA
out of the node 6 cells below top of stack, 7.5μA into the
node 6 cells above bottom of stack, and 23.5μA into the
bottom of stack node. All other intermediate node cur-
rents are zero. This is shown graphically in Figure 15. For
the specific case of a 12-cell stack, this reduces to only
23.5µA out of the top of stack node and 23.5µA into the
bottom of stack node.
TOP OF STACK
+
CELL N
+
CELL N – 6
+
CELL N – 7
+
CELL N – 12
23.5µA
ALL
ZERO
C6
C5
C4
C3
C2
C1
V^–
LTC3300-1
16µA
TOS = 1
3
7.5µA
ALL
ZERO
0µA
C6
C5
C4
C3
C2
C1
V^–
LTC3300-1
16µA
7.5µA
3
+
CELL 12
+
CELL 7
0µA
ALL
ZERO
3
C6
LTC3300-1
C5
C4
C3
C2
C1
V^–
16µA
7.5µA
+
CELL 6
7.5µA
C6
3
LTC3300-1
C5
+
CELL 1
ALL
ZERO
C4
C3
C2
C1
V^–
16µA
7.5µA
BOTTOM OF STACK
33001 F15
23.5µA
Figure 15. Stack Terminal Currents in Shutdown
36
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33001f