LTC3300-1 Datasheet, PDF (27/44 Pages) Linear Technology – High Effciency Bidirectional Multicell Battery Balancer

LTC3300-1
OPERATION
The first 12 bits of the 16-bit balance command are used
to indicate which balancer (or balancers) is active and in
which direction (charge or discharge). Each of the 6 cell
balancers is controlled by 2 bits of this data per Table 5.
The balancing algorithm for a given cell is:
Charge Cell n: Ramp up to I_PEAK in secondary winding,
ramp down to I_ZERO in primary winding. Repeat.
Discharge Cell n (Synchronous): Ramp up to Ipeak in
primary winding, ramp down to I_ZERO in secondary
winding. Repeat.
Table 5. Cell Balancer Control Bits
Dn A
Dn B
Balancing Action (n = 1 to 6)
0
0
None
0
1
Discharge Cell n (Nonsynchronous)
1
0
Discharge Cell n (Synchronous)
1
1
Charge Cell n
For nonsynchronous discharging of cell n, both the sec-
ondary winding gate drive and (zero) current sense amp
are disabled. The secondary current will conduct either
through the body diode of the secondary switch (if pres-
ent) or through a substitute Schottky diode. The primary
will only turn on again after the secondary winding Volt-
sec clamp times out. In a bidirectional application with a
secondary switch, it may be possible to achieve slightly
higher discharge efficiency by opting for nonsynchronous
discharge mode (if the gate charge savings exceed the
added diode drop losses) but the balancing current will be
less predictable because the secondary winding Volt-sec
clamp must be set longer than the expected time for the
current to hit zero in order to guarantee no current reversal.
In the case where a Schottky diode replaces the secondary
switch, it is possible to build a undirectional discharge-only
balancing application charging an isolated auxiliary cell
as shown in Figure 19 in the Typical Applications section.
In the CTRL = 1 application of Figure 7 employing a single
transformer which can only balance one cell at a time, any
command requesting simultaneous balancing of more than
one cell will be ignored. All active balancing will be turned
off if an Execute Balance Command is subsequently written.
The last 4 bits of the 16-bit balance command are used
for packet error checking (PEC). The 16 bits of write data
(12-bit message plus 4-bit CRC) are input to a cyclic re-
dundancy check (CRC) block employing the International
Telecommunication Union CRC-4 standard characteristic
polynomial:
x⁴ + x + 1
In the write data, the 4-bit CRC appended to the message
must be selected such that the remainder of the CRC divi-
sion is zero. Note that the CRC bits in the Write Balance
Command are inverted. This was done so that an “all zeros”
command is invalid. The LTC3300-1 will ignore the write
data if the remainder is not zero and the internal command
holding register will be cleared which can be verified on
readback. The current balance command being executed
(from the last previously successful write) will continue,
but all active balancing will be turned off if an Execute Bal-
ance Command is subsequently written. For information
on how to calculate the CRC including an example, refer
to the Applications Information section.
Readback Balance Command
The bit mapping for Readback Balance Command is identi-
cal to that for Write Balance Command. If the command
bits program Readback Balance Command, successive
16-bit previously written data (latched in 12-bit message
plus newly calculated 4-bit CRC) are shifted out in the
same order bitwise (MSB first) starting with the lowest
LTC3300-1 in the stack and proceeding up the stack. Thus,
the sequence of outcoming data during readback is:
Command data (bottom chip), Command data (2nd chip
from bottom), …, Command data (top chip)
This command allows for microprocessor verification of
written commands before executing. Note that the CRC
bits in the Readback Balance Command are also inverted.
This was done so that an “all zeros” readback is invalid.
For more information www.linear.com/product/LTC3300-1
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