LTC3335_15 Datasheet, PDF (25/28 Pages) Linear Technology – Nanopower Buck-Boost DC/DC with Integrated Coulomb Counter

LTC3335
Applications Information
either a repeat START or a STOP condition. If a repeat
START condition is initiated by the master, the LTC3335,
or any other chip on the I²C bus, can then be addressed.
The LTC3335 will remember, but not act on, the last input
of valid data that it received at each subaddress location.
This cycle can also continue indefinitely. Once all chips on
the bus have been addressed and sent valid data, a global
STOP can be sent and the LTC3335 will immediately update
all of its command registers with the most recent pending
data that it had previously received.
Bus Read Operation
The LTC3335 contains 2 readable registers. One is read
only and contains alarm information (Register D). The
other contains accumulated battery discharge information
(Register C) which may be both written and read back by
the bus master.
Only one subaddressed data register is accessible during
each bus read operation. The data returned by the LTC3335
is from the data register pointed to by the contents of the
subaddress pointer register. The pointer register contents
are determined by the previous bus write operation.
In preparation for a bus read operation, it may be ad-
vantageous for a bus master to prematurely terminate a
write transaction with a STOP or repeat START condition
after transmitting only an odd number of bytes. The last
transmitted byte then represents a pointer to the register
of interest for the subsequent bus read operation.
The bus master reads status data from the LTC3335
with a START or repeat START condition followed by the
LTC3335 read address. If the read address matches that
of the LTC3335, the LTC3335 returns an acknowledge.
Following the acknowledgement of its read address, the
LTC3335 returns one bit of status information for each of
the next eight clock cycles from the register selected by
the subaddress pointer. Additional clock cycles from the
master after the single data byte has been read will leave
the SDA line high (0xFF transmitted). The LTC3335 will
never acknowledge any bytes during a bus read operation
with the exception of its read address.
To read the same register again, the transaction may be
repeated starting with a START followed by the LTC3335
read address. It is not necessary to rewrite the subaddress
pointer register if the subaddress has not changed. To read
a different register, a write transaction must be initiated
with a START or repeat START followed by the LTC3335
write address and subaddress pointer byte before the read
transaction may be repeated.
When the contents of the subaddress pointer register
point to write-only command register (A, B, E), the data
returned in a bus read operation is the pending command
data at that location if it had been modified since the last
STOP condition. After a STOP condition, all pending data
is copied to the command registers for immediate effect.
When the contents of the subaddress pointer register
point to the writable and readable command register C,
the data returned in a bus read operation is data at that
location, not the pending command data from previous
write operation. After a STOP condition, all pending data
is copied to the command registers for immediate effect
and a following read operation can read the effect.
When the contents of the subaddress pointer register
point to the read-only alarm register D, the data returned
is a snapshot of the state of the LTC3335 at a particular
instant in time. If no interrupt requests are pending, the
status data is sampled when the LTC3335 acknowledges
its read address, just before the LTC3335 begins data
transmission during a bus read operation. When an alarm/
fault occurs, the IRQ pin is driven low and data is latched
in the alarm register D at that moment. Any subsequent
read operation from register D will return this frozen data
to facilitate determination of the cause of the interrupt
request. After the bus master clears the LTC3335 interrupt
request (E[0] =1), the status latches are cleared. Bus read
operations will then again return either a snapshot of the
data at the read address acknowledge, or at the time of
the next interrupt assertion, whichever comes first.
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3335p
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