LTC3335_15 Datasheet, PDF (23/28 Pages) Linear Technology – Nanopower Buck-Boost DC/DC with Integrated Coulomb Counter

LTC3335
Applications Information
Example 2: A Panasonic CR2032 primary cell (3.0V nomi-
nal, 225mA • hr) is powering a 5V output and the I_PEAK
setting is 5mA. The appropriate pre-scaler is M=7. From
curve G44 in the Typical Performance Characteristics, the
nominal error for continuous switching under these condi-
tions is –22%. In this case the raw coulomb count error
is significant if left unadjusted. Suppose after 6 months
of battery service, the accumulated charge register C[7:0]
reads 28h(hex) or 40(decimal). The raw and adjusted
coulomb counts are given by:
Raw coulomb count = q_{LSB_7} • C[7:0] = 140.6mA • hr/27
• 40 = 43.9mA • hr
Adjusted coulomb count = 43.9mA • hr • (1/(1-.22) +
(5.96mA • hr) • 0.5 = 59.3mA • hr
The adjusted coulomb count will be much closer to the
actual coulombs and the preset alarm level (if used) can
be appropriately adjusted to compensate for this:
Adjusted Alarm Set Level = [(Desired Alarm Level/100) •
Q_BAT) - (5.96mAhr • Years)] * (1 - Error/100) • 1/q_{LSB_M}
I²C Interface
The LTC3335 communicates with a bus master using the
standard I²C 2-wire serial interface. The Timing Diagram
shows the relationship of the signals on the bus. The two
bus lines, SDA and SCL, must be HIGH when the bus is
not in use. External pull-up resistors are required on these
lines. The I²C control signals, SDA and SCL, are scaled
internally to the DV_CC supply. DV_CC should be connected
to the same power supply as the bus pull-up resistors.
The I²C port has an undervoltage lockout on the DV_CC pin.
When DV_CC is below approximately 1.3V, the I²C serial
port is disabled.
Bus Speed
The I²C port is designed to operate at speeds of up to
400kHz. It has built-in timing delays to ensure correct
operation when addressed from an I²C compliant master
device. It also contains input filters designed to suppress
glitches.
START and STOP Conditions
A bus master signals the beginning of communications
by transmitting a START condition. A START condition is
generated by transitioning SDA from HIGH to LOW while
SCL is HIGH. The master may transmit either the slave
write or the slave read address. Once data is written to
the LTC3335, the master may transmit a STOP condi-
tion which commands the LTC3335 to act upon its new
command set. A STOP condition is sent by the master by
transitioning SDA from LOW to HIGH while SCL is HIGH.
Byte Format
Each frame sent to or received from the LTC3335 must
be eight bits long, followed by an extra clock cycle for the
acknowledge bit. The data must be sent to the LTC3335
most significant bit (MSB) first.
Master and Slave Transmitters and Receivers
Devices connected to an I²C bus may be classified as
either master or slave. A typical bus is composed of one
or more master devices and a number of slave devices.
Some devices are capable of acting as either a master or
a slave, but they may not change roles while a transaction
is in progress.
The transmitter/receiver relationship is distinct from that
of master and slave. The transmitter is responsible for
control of the SDA line during the eight bit data portion
of each frame. The receiver is responsible for control of
SDA during the ninth and final acknowledge clock cycle
of each frame.
All transactions are initiated by the master with a START
or repeat START condition. The master controls the active
(falling) edge of each clock pulse on SCL, regardless of its
status as transmitter or receiver. The slave device never
brings SCL LOW.
The LTC3335 does not clock stretch and will never hold
SCL LOW under any circumstance.
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3335p
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