LTC3335_15 Datasheet, PDF (15/28 Pages) Linear Technology – Nanopower Buck-Boost DC/DC with Integrated Coulomb Counter

LTC3335
Operation
V_OUT Power Good
A power good comparator is provided for the V_OUT output.
The PGOOD pin transitions high when the LTC3335 first
goes to sleep, indicating that V_OUT has reached regulation.
It transitions low when V_OUT falls to 92% (typical) of its
average value at regulation.
Coulomb Counter
The LTC3335 integrates a precision coulomb counter to
monitor the accumulated charge that is transferred from
the battery whenever the buck-boost converter is deliver-
ing current to V_OUT. The buck-boost converter operates
as an H-Bridge for all BAT/V_OUT conditions when not in
sleep (see Figure 3). Switches A and C turn ON at the
beginning of each burst cycle. Inductor current ramps to
I_PEAK and then switches A and C turn OFF. Switches B and
D then turn ON until the inductor current ramps to zero.
This cycle repeats until V_OUT reaches the sleep threshold.
I_PEAK
Q_VIN
AC
BD
AC
BD
I_L
SLEEP
BURST
SLEEP
0
t_AC
t_AC
TIME
Figure 3
3335 F03
If I_PEAK and the switch AC(ON) time (t_AC) are both known,
then the BAT discharge coulombs (shaded area in Figure
3) can be calculated by counting the number of AC(ON)
cycles and multiplying by the charge per AC(ON) cycle
given in Formula (1) below:
q_AC(ON)
=
I_PEAK •
2
t
AC
(1)
When the buck-boost is operating, the LTC3335 measures
the actual AC(ON) time relative to a full scale ON time (t_FS,
approximately 11.74µs) which is internally adjusted to
compensate for errors in the actual selected I_PEAK value
due to supply, temperature, and process variations. This
results in a very accurate “measurement” of the charge
transferred from the battery during each AC(ON) cycle.
This is represented as an 8-bit number which is then
added to the previous accumulated total coulomb count
each time switches A and C turn on. The adder carry bit
is the clock for the remaining 42-bit ripple counter. When
the buck-boost is in sleep, the coulomb counter holds its
state and draws no current.
There are a total of 50 bits in the coulomb counter chain,
but only the 8 MSBs may be read back over I²C. These
bits are contained in register C, the accumulated charge
register. The amount of charge represented by the least
significant bit (q_LSB) of the accumulated charge register
(Register C) is given in the Electrical Characteristics section
for all 8 I_PEAK settings for the case of the default pre-scalar
setting (M = 0, which uses the full length of the internal
counter). See Choosing Coulomb Counter Prescalar M
section for instructions on calculating q_LSB with a nonzero
prescalar setting.
I²C Interface
The 7-bit hard-wired I²C address of the LTC3335 is
1100100[R/W]. The LTC3335 is a slave-only device mean-
ing that the serial clock line (SCL) is only an input while
the serial data line (SDA) is bidirectional.
Internal Registers
The LTC3335 has 5 internal subaddressed I²C registers,
as shown in Table 3. Registers A, B, and E are write only,
Register C is read/write, and Register D is read only, as
shown in Tables 4, 5, and 6, respectively.
Table 3. Register Map
SUB REGISTER REGISTER
ADDRESS NAME DESCRIPTION
R/W DEFAULT
01h
A
V_OUT selection and
W
00h
prescaler selection
02h
B Alarm threshold
W
FFh
03h
C Accumulated charge R/W
00h
04h
D Alarms
R
00h
05h
E
Interrupt register
W
00h
R = read, W = write
LINEAR_FoT_{r m}E_oC_{re i}H_nfoN_rmO_atiL_onO_wwG_wY_.lineC_ar.cO_omN_/LTF_C3I₃D₃₅ENTIAL
3335p
15