LTC3335_15 Datasheet, PDF (17/28 Pages) Linear Technology – Nanopower Buck-Boost DC/DC with Integrated Coulomb Counter

LTC3335
Operation
Alarm
An alarm causes the IRQ pin to be pulled low. The user
can read register D to determine what caused the alarm.
The alarm can then be cleared by writing 1 to bit E[0].
The clear interrupt bit is self-clearing after taking action
on the IRQ pin.
When clearing an alarm, if another alarm trips, the IRQ
pin will go high for 1µs (typical) before returning low
again. During this time, the clear interrupt bit E[0] is also
reset to zero.
There are 3 different fault/alarm conditions:
1) An AC(ON) time overflow (D[0] is high) due to an im-
properly chosen inductor value timing out the AC(ON)
time measurement. After the alarm is cleared the IRQ pin
goes high and stays high at least until the next AC(ON)
pulse is measured. A different inductor or I_PEAK setting
needs to be chosen to keep the alarm from continuously
tripping.
2) A coulomb counter overflow (D[1] is high) due to an
improperly chosen prescalar value causing the ripple
counter to overflow. After the alarm is cleared the IRQ
pin is released for 1µs and later pulled low again un-
less register C is overwritten with a lower value and the
prescaler is changed.
3) The preset alarm level is reached (D[2] is high) when
the 8 MSBs of the ripple counter are equal to or higher
than the 8 bits in register B. The user should increase
the alarm threshold in register B and then write bit E[0]
to 1 to clear the alarm.
The alarm threshold is only checked after each AC(ON)
pulse or when a write to register C is done via I²C.
Therefore, if bit E[0] is set to 1 to clear an alarm inter-
rupt without also changing the contents of register B
and/or C, and this occurs during a long sleep time, the
IRQ pin is cleared and doesn't go back low again until
the next AC(ON) pulse.
Power Up Sequence
When the battery is first inserted and the internal circuits
are powering up, the LTC3335 resets all registers to their
default states, including the adder and the ripple counter.
The buck-boost requires a finite start up time until V_OUT
charges up to the target value. When V_OUT reaches the
PGOOD threshold, the PGOOD pin goes high. During the
entire start-up sequence, the coulomb counter counts
correctly.
If the EN pin is pulled low, the buck-boost is disabled.
However, the digital register contents of the coulomb
counter remain saved in memory. When re-enabled, the
coulomb counter continues counting from where it left off.
The digital registers are reset only if the BAT voltage is lost.
DV_CC I²C Power Supply
The DV_CC pin can be connected to BAT, to V_OUT, or to
a separate external supply between 1.8V and 5.5V. A
power-on-reset circuit monitors the DV_CC supply. For
DV_CC voltages below 1.3V (typical), the I²C interface is
disabled. The user can't read or write, but the coulomb
counter is still fully functional.
If the BAT voltage is lost, the coulomb counter and the
buck-boost are switched off and the contents of all digital
registers are lost. The full functionality of the coulomb
counter is guaranteed for BAT voltages equal to or greater
than 1.8V.
If DV_CC is connected to V_OUT or to a separate external
supply, the coulomb counter is still fully functional, even
if V_OUT = 0V such as during startup.
For the external pull-up resistors on SDA and SCL pins,
10kΩ is recommended.
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3335p
17