LTC3335_15 Datasheet, PDF (12/28 Pages) Linear Technology – Nanopower Buck-Boost DC/DC with Integrated Coulomb Counter

LTC3335
Pin Functions
SDA (Pin 1 ): Serial Data Input/Output for the I²C Serial
Port. The I²C input levels are scaled with respect to DV_CC
for I²C compliance. Do not float.
DV_CC (Pin 2): Supply Rail for the I²C Serial Bus. DV_CC
sets the reference level of the SDA and SCL pins for I²C
compliance. The external I²C pull-up resistors on SDA and
SCL should connect to DV_CC. Depending on the particular
application, DV_CC can be connected to BAT, to V_OUT, or
to a separate external supply between 1.8V and 5.5V. In
most applications DV_CC will be connected to the I/O rail
of the microprocessor reading the I²C registers.
OUT[2:0] (Pin 3, 4, 5): V_OUT Voltage Select Bits. Tie high
to BAT or low to GNDA to select the desired V_OUT (see
Table 2). Do not float.
GNDD (Pin 6): Signal ground for internal digital circuits.
Connect to GNDA and PGND.
BAT (Pin 7): Buck-Boost Input Voltage Sense Pin. Con-
nect to PBAT.
PBAT (Pin 8): Buck-Boost Input Voltage. This pin is the
power input of the regulator. Connect to BAT.
SW1 (Pin 9): Buck-Boost Switch Pin. Connected to internal
power switches A and B. Connect an inductor (value in
Table 9) between this node and SW2.
SW2 (Pin 10): Buck-Boost Switch Pin. Connected to internal
power switches C and D. Connect an inductor (value in
Table 8) between this node and SW1.
PV_OUT (Pin 11): Buck-Boost Output Voltage. This pin is
the power output of the regulator. Connect to V_OUT.
V_OUT (Pin 12): Buck-Boost Output Voltage Sense Pin.
Connect to PV_OUT.
IPK[2:0] (Pin 15, 14, 13): Peak Input Current Select Bits.
Tie high to BAT or low to GNDA to select desired I_PEAK
(see Table 1). Do not float.
EN (Pin 16): Buck-Boost Enable Input. Tie high to BAT or
low to GNDA to enable/disable the buck-boost. If EN is
pulled low, the buck-boost is disabled but internal register
contents are saved. Do not float.
GNDA (Pin 17): Signal ground for internal analog circuits.
Connect to GNDD and PGND.
PGOOD (Pin 18): Power Good Output. Logic level output
referenced to DV_CC. This output is pulled low after the
buck-boost is enabled and remains low until V_OUT reaches
regulation.
IRQ (Pin 19): Interrupt Output. Logic level output referenced
to DV_CC. Active low. This pin is normally logic high but
will transition low when the preset alarm level is reached
or if there is an overflow in either the coulomb counter or
the AC(ON) time measurement.
SCL (Pin 20): Serial Clock Input for the I²C Serial Port.
The I²C input levels are scaled with respect to DV_CC for
I²C compliance. Do not float.
PGND (Exposed Pad Pin 21): Power Ground. The Exposed
Pad connects to the sources of the internal N-channel
power MOSFETs. It should be soldered to the PCB and
electrically connected to system ground through the short-
est and lowest impedance connection possible. Connect
to GNDA and GNDD.
3335p
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