LTC3335_15 Datasheet, PDF (24/28 Pages) Linear Technology – Nanopower Buck-Boost DC/DC with Integrated Coulomb Counter

LTC3335
Applications Information
The master device begins each I²C transaction as the
transmitter and the slave device begins each transaction
as the receiver. For bus write operations, the master acts
as the transmitter and the slave acts as receiver for the
duration of the transaction. For bus read operations, the
master and slave exchange transmit/receive roles following
the address frame for the remainder of the transaction.
Acknowledge
The acknowledge signal (ACK) is used for handshaking
between the transmitter and receiver. When the LTC3335
is written to, it acknowledges its write address as well as
the subsequent data bytes as a slave receiver. When it is
read from, the LTC3335 acknowledges its read address
as a slave receiver. The LTC3335 then changes to a slave
transmitter and the master receiver may optionally acknowl-
edge receipt of the following data byte from the LTC3335.
The acknowledge related clock pulse is always generated by
the bus master. The transmitter (master or slave) releases
the SDA line (HIGH) during the acknowledge clock cycle.
The receiver (slave or master) pulls down the SDA line
during the acknowledge clock pulse so that it is a stable
LOW during the HIGH period of this clock pulse.
When the LTC3335 is read from, it releases the SDA line
after the eighth data bit so that the master may acknowl-
edge receipt of the data. The I²C specification calls for a
not acknowledge (NACK) by the master receiver following
the last data byte during a read transaction. Upon receipt
of the NACK, the slave transmitter is instructed to release
control of the bus. Because the LTC3335 only transmits
one byte of data under any circumstance, a master ac-
knowledging or not acknowledging the data sent by the
LTC3335 has no consequence. The LTC3335 will release
the bus in either case.
Slave Address
The LTC3335 responds to a 7-bit address which has been
factory programmed to 1100100[R/W]. The LSB of the
address byte, known as the read/write bit, should be 0
when writing data to the LTC3335, and 1 when reading
data from it. Considering the address an 8-bit word, then
the write address is 0xC8, and the read address is 0xC9.
The LTC3335 will acknowledge both its read and write
addresses.
Subaddressed Access
The LTC3335 has three write registers for control input,
one read register for alarm reporting and one read/write
register for the accumulated battery discharge. They
are accessed by the I²C port via a subaddressed pointer
system where each subaddress value points to one of the
five control or status registers within the LTC3335. See
Table 3 for subaddress information.
The subaddress pointer is always the first byte written
immediately following the LTC3335 write address dur-
ing bus write operations. The subaddress pointer value
persists after the bus write operation and will determine
which data byte is returned by the LTC3335 during any
subsequent bus read operations.
Bus Write Operation
The bus master initiates communication with the LTC3335
with a START condition and the LTC3335’s write address.
If the address matches that of the LTC3335, the LTC3335
returns an acknowledge. The bus master should then de-
liver the subaddress. The subaddress value is transferred
to a special pointer register within the LTC3335 upon the
return of the subaddress acknowledge bit by the LTC3335.
If the master wishes to continue the write transaction, it
may then deliver the data byte. The data byte is transferred
to an internal pending data register at the location of the
subaddress pointer when the LTC3335 acknowledges the
data byte. The LTC3335 is then ready to receive a new
subaddress, optionally repeating the [SUBADDRESS]
[DATA] cycle indefinitely. After the write address, the odd
position bytes always represent a subaddress pointer as-
signment and the even position bytes always represent data
to be stored at the location referenced by the subaddress
pointer. The master may terminate communication with
the LTC3335 after any even or odd number of bytes with
3335p
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