1032E1111 Datasheet, PDF (9/16 Pages) Lattice Semiconductor – High-Density Programmable Logic

Specifications ispLSI and pLSI 1032E
Internal Timing Parameters¹
PARAM. #
DESCRIPTION
Outputs
tob
49 Output Buffer Delay
tsl
50 Output Buffer Delay, Slew Limited Adder
toen
todis
tgoe
51 I/O Cell OE to Output Enabled
52 I/O Cell OE to Output Disabled
53 Global OE
Clocks
tgy0
54 Clk Delay, Y0 to Global GLB Clk Line (Ref. clk)
tgy1/2
tgcp
tioy2/3
55 Clk Delay, Y1 or Y2 to Global GLB Clk Line
56 Clk Delay, Clock GLB to Global GLB Clk Line
57 Clk Delay, Y2 or Y3 to I/O Cell Global Clk Line
tiocp
58 Clk Delay, Clk GLB to I/O Cell Global Clk Line
Global Reset
tgr
59 Global Reset to GLB and I/O Registers
1. Internal Timing Parameters are not tested and are for reference only.
-125
-100
UNITS
MIN. MAX. MIN. MAX.
– 1.3
– 9.9
– 4.3
– 4.3
– 2.7
– 2.0 ns
– 10.0 ns
– 5.1 ns
– 5.1 ns
– 3.9 ns
1.4 1.4 1.5 1.5 ns
1.4 1.4 1.5 1.5 ns
0.8 1.8 0.8 1.8 ns
0.0 0.0 0.0 0.0 ns
0.8 1.8 0.8 1.8 ns
– 2.8
– 4.3 ns
Table 2-0037A/1032E
9