1032E1111 Datasheet, PDF (13/16 Pages) Lattice Semiconductor – High-Density Programmable Logic

Specifications ispLSI and pLSI 1032E
Pin Description
NAME
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
I/O 32 - I/O 35
I/O 36 - I/O 39
I/O 40 - I/O 43
I/O 44 - I/O 47
I/O 48 - I/O 51
I/O 52 - I/O 55
I/O 56 - I/O 59
I/O 60 - I/O 63
PLCC PIN
NUMBERS
26, 27, 28, 29,
30, 31, 32, 33,
34, 35, 36, 37,
38, 39, 40, 41,
45, 46, 47, 48,
49, 50, 51, 52,
53, 54, 55, 56,
57, 58, 59, 60,
68, 69, 70, 71,
72, 73, 74, 75,
76, 77, 78, 79,
80, 81, 82, 83,
3, 4, 5, 6,
7, 8, 9, 10,
11, 12, 13, 14,
15, 16, 17, 18
TQFP PIN
NUMBERS
DESCRIPTION
17, 18, 19, 20, Input/Output Pins - These are the general purpose I/O pins used by the logic
21, 22, 23, 28, array.
29, 30, 31, 32,
33, 34, 35, 36,
40, 41, 42, 43,
44, 45, 46, 47,
48, 53, 54, 55,
56, 57, 58, 59,
67, 68, 69, 70,
71, 72, 73, 78,
79, 80, 81, 82,
83, 84, 85, 86,
90, 91, 92, 93,
94, 95, 96, 97,
98, 3, 4, 5,
6, 7, 8, 9
GOE 0/IN 4³ 67
66
This is a dual function pin. It can be used either as Global Output Enable for
all I/O cells or it can be used as a dedicated input pin.
GOE 1/IN 5³ 84
87
This is a dual function pin. It can be used either as Global Output Enable for
all I/O cells or it can be used as a dedicated input pin.
IN 6, IN 7
ispEN/NC^1,2
2, 19
23
SDI/IN 0²
25
MODE/IN 1² 42
SDO/IN 2²
44
SCLK/IN 3²
61
RESET
24
Y0
20
Y1
66
Y2
63
Y3
62
89, 10
14
16
37
39
60
15
11
65
62
61
Dedicated input pins to the device.
Input - Dedicated in-system programming enable input pin. This pin is
brought low to enable the programming mode. The MODE, SDI, SDO and
SCLK options become active.
Input - This pin performs two functions. When ispEN is logic low, it functions
as an input pin to load programming data into the device. SDI/IN 0 is also
used as one of the two control pins for the isp state machine. It is a
dedicated input pin when ispEN is logic high.
Input - This pin performs two functions. When ispEN is logic low, it functions
as pin to control the operation of the isp state machine. It is a dedicated
input pin when ispEN is logic high.
Output/Input - This pin performs two functions. When ispEN is logic low, it
functions as an output pin to read serial shift register data. It is a dedicated
input pin when ispEN is logic high.
Input - This pin performs two functions. When ispEN is logic low, it functions
as a clock pin for the Serial Shift Register. It is a dedicated input pin when
ispEN is logic high.
Active Low (0) Reset pin which resets all of the GLB and I/O registers in the
device.
Dedicated Clock input. This clock input is connected to one of the clock
inputs of all of the GLBs on the device.
Dedicated Clock input. This clock input is brought into the clock distribution
network, and can optionally be routed to any GLB on the device.
Dedicated Clock input. This clock input is brought into the clock distribution
network, and can optionally be routed to any GLB and/or any I/O cell on the
device.
Dedicated Clock input. This clock input is brought into the clock distribution
network, and can optionally be routed to any I/O cell on the device.
GND
VCC
NC¹
1, 22, 43, 64
21, 65
13, 38, 63, 88 ^{Ground (GND)}
12, 64
Vcc
1, 2,
26, 27,
51, 52,
76, 77,
24, 25, No connect.
49, 50,
74, 75,
99, 100
1. NC pins are not to be connected to any ative signals, Vcc or GND.
2. Pins have dual function capability for ispLSI 1032E only.
3. Pins have dual function capability which is software selectable.
Table 2-0002A/1032E
13