1032E1111 Datasheet, PDF (5/16 Pages) Lattice Semiconductor – High-Density Programmable Logic

Specifications ispLSI and pLSI 1032E
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER ^{TEST 4} #²
COND.
DESCRIPTION¹
-125
-100
UNITS
MIN. MAX. MIN. MAX.
tpd1
A
tpd2
A
fmax (Int.) A
fmax (Ext.) –
fmax (Tog.) –
tsu1
–
1 Data Propagation Delay, 4PT Bypass, ORP Bypass
2 Data Propagation Delay, Worst Case Path
3 Clock Frequency with Internal Feedback ³
4
Clock
Frequency
with
External
Feedback
(
1
tsu2 +
) _tco1
5
Clock
Frequency,
Max.
Toggle
(
1
twh +
) _tw1
6 GLB Reg. Setup Time before Clock,4 PT Bypass
– 7.5 – 10.0
– 10.0 – 12.5
125 – 100 –
91.0 – 71.0 –
167 – 125 –
5.0 – 7.0 –
ns
ns
MHz
MHz
MHz
ns
tco1
A 7 GLB Reg. Clock to Output Delay, ORP Bypass
– 5.0 – 6.0 ns
th1
– 8 GLB Reg. Hold Time after Clock, 4 PT Bypass
0.0 – 0.0 –
ns
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
twl
– 9 GLB Reg. Setup Time before Clock
– 10 GLB Reg. Clock to Output Delay
– 11 GLB Reg. Hold Time after Clock
A 12 Ext. Reset Pin to Output Delay
– 13 Ext. Reset Pulse Duration
B 14 Input to Output Enable
C 15 Input to Output Disable
B 16 Global OE Output Enable
C 17 Global OE Output Disable
– 18 External Synchronous Clock Pulse Duration, High
– 19 External Synchronous Clock Pulse Duration, Low
6.0 – 8.0 –
ns
– 6.0 – 7.0 ns
0.0 – 0.0 –
ns
– 10.0 – 13.5 ns
5.0 – 6.5 –
ns
– 12.0 – 15.0 ns
– 12.0 – 15.0 ns
– 7.0 – 9.0 ns
– 7.0 – 9.0 ns
3.0 – 4.0 –
ns
3.0 – 4.0 –
ns
tsu3
– 20 I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3)
3.0 – 3.5 –
ns
th3
– 21 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
0.0 – 0.0 –
ns
1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
Table 2-0030A/1032E
5