1032E1111 Datasheet, PDF (12/16 Pages) Lattice Semiconductor – High-Density Programmable Logic

Specifications ispLSI and pLSI 1032E
Maximum GRP Delay vs GLB Loads
6.0
ispLSI and pLSI 1032E-70
5.0
ispLSI and pLSI 1032E-80
ispLSI and pLSI 1032E-90/100
4.0
ispLSI and pLSI 1032E-125
3.0
2.0
1.0
14
8
16
GLB Load
32
GRP/GLB/1032E
Power Consumption
Power consumption in the ispLSI and pLSI 1032E device used. Figure 3 shows the relationship between power
depends on two primary factors: the speed at which the and operating speed.
device is operating, and the number of product terms
Figure 3. Typical Device Power Consumption vs fmax
350
300
ispLSI and pLSI 1032E
250
200
150
100
0
20
40 60
80 100 125 150
fmax (MHz)
Notes: Configuration of eight 16-bit counters
Typical current at 5V, 25°C
I _CC can be estimated for the ispLSI and pLSI 1032E using the following equation:
I _CC(mA) = 15 + (# of PTs * 0.59) + (# of nets * Max freq * 0.0078)
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
The I_CC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of four GLB
loads on average exists. These values are for estimates only. Since the value of I _CC is sensitive to operating
conditions and the program in the device, the actual I _CC should be verified.
0127/1032E
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