1032E1111 Datasheet, PDF (11/16 Pages) Lattice Semiconductor – High-Density Programmable Logic

Specifications ispLSI and pLSI 1032E
ispLSI and pLSI 1032E Timing Model
I/O Cell
GRP
GLB
Feedback
Ded. In
I/O Pin
(Input)
#59
#28
I/O Reg Bypass
#22
Input
D ^Register Q
RST
#23 - 27
Reset
GRP4
#30
GRP Loading
Delay
#29, 31 - 33
#34 Comb 4 PT Bypass
Reg 4 PT Bypass
#35
20 PT
XOR Delays
#36 - 38
#59
GLB Reg Bypass
#39
GLB Reg
Delay
D
Q
RST
#40 - 43
ORP
I/O Cell
ORP Bypass
#48
ORP
Delay
#47
#49, 50
I/O Pin
(Output)
#51, 52
Clock
Distribution
Control _RE
PTs _OE
Y1,2,3
#55 - 58
#44 - 46 CK
0491
#54
Y0
GOE 0,1
#53
Derivations of tsu, th and tco from the Product Term Clock¹
tsu
= Logic + Reg su - Clock (min)
= (tiobp + tgrp4 + t20ptxor) + (tgsu) – (tiobp + tgrp4 + tptck(min))
= (#22 + #30 + #37) + (#40) – (#22 + #30 + #46)
2.2 ns = (0.3 + 2.0 + 5.0) + (0.1) – (0.3 + 2.0 + 2.9)
th
= Clock (max) + Reg h - Logic
= (tiobp + tgrp4 + tptck(max)) + (tgh) – (tiobp + tgrp4 + t20ptxor)
= (#22 + #30 + #46) + (#41) - (#22 + #30 + #37)
3.5 ns = (0.3 + 2.0 + 4.0) + (4.5) – (0.3 + 2.0 + 5.0)
tco
= Clock (max) + Reg co + Output
= (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob)
= (#22 + #30 + #46) + (#42) + (#47 + #49)
10.9 ns = (0.3 + 2.0 + 4.0) + (2.3) + (1.0 + 1.3)
Derivations of tsu, th and tco from the Clock GLB ¹
tsu
= Logic + Reg su - Clock (min)
= (tiobp + tgrp4 + t20ptxor) + (tgsu) – (tgy0(min) + tgco + tgcp(min))
= (#22 + #30 + #37) + (#40) – (#54 + #42 + #56)
2.9 ns = (0.3 + 2.0 + 5.0) + (0.1) – (1.4 + 2.3 + 0.8)
th
= Clock (max) + Reg h - Logic
= (tgy0(max) + tgco + tgcp(max)) + (tgh) – (tiobp + tgrp4 + t20ptxor)
= (#54 + #42 + #56) + (#41) – (#22 + #30 + #37)
2.7 ns = (1.4 + 2.3 + 1.8) + (4.5) – (0.3 + 2.0 + 5.0)
tco
= Clock (max) + Reg co + Output
= (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob)
= (#54 + #42 + #56) + (#42) + (#47 + #49)
5.5 ns = (1.4 + 2.3 + 1.8) + (2.3) + (1.0 + 1.3)
1. Calculations are based upon timing specifications for the ispLSI and pLSI 1032E-125.
Table 2-0042a/1032E
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