1032E1111 Datasheet, PDF (7/16 Pages) Lattice Semiconductor – High-Density Programmable Logic

Specifications ispLSI and pLSI 1032E
Internal Timing Parameters¹
PARAM. # ²
DESCRIPTION
Inputs
tiobp
tiolat
tiosu
tioh
tioco
tior
tdin
GRP
tgrp1
tgrp4
tgrp8
22 I/O Register Bypass
23 I/O Latch Delay
24 I/O Register Setup Time before Clock
25 I/O Register Hold Time after Clock
26 I/O Register Clock to Out Delay
27 I/O Register Reset to Out Delay
28 Dedicated Input Delay
29 GRP Delay, 1 GLB Load
30 GRP Delay, 4 GLB Loads
31 GRP Delay, 8 GLB Loads
tgrp16 32 GRP Delay, 16 GLB Loads
tgrp32 33 GRP Delay, 32 GLB Loads
GLB
t4ptbpc 34 4 Prod.Term Bypass Path Delay (Combinatorial)
t4ptbpr 35 4 Prod. Term Bypass Path Delay (Registered)
t1ptxor 36 1 Prod.Term/XOR Path Delay
t20ptxor 37 20 Prod. Term/XOR Path Delay
txoradj 38 XOR Adjacent Path Delay ³
tgbp 39 GLB Register Bypass Delay
tgsu
tgh
40 GLB Register Setup Time before Clock
41 GLB Register Hold Time after Clock
tgco
tgro
tptre
tptoe
tptck
42 GLB Register Clock to Output Delay
43 GLB Register Reset to Output Delay
44 GLB Prod.Term Reset to Register Delay
45 GLB Prod. Term Output Enable to I/O Cell Delay
46 GLB Prod. Term Clock Delay
ORP
torp
torpbp
47 ORP Delay
48 ORP Bypass Delay
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
-125
-100
UNITS
MIN. MAX. MIN. MAX.
– 0.3 – 0.3 ns
– 1.9 – 2.3 ns
3.0 – 3.5 – ns
0.0 – 0.0 – ns
– 4.6 – 5.0 ns
– 4.6 – 5.0 ns
– 2.3 – 2.7 ns
– 1.8
– 2.0
– 2.3
– 2.8
– 3.8
– 1.9 ns
– 2.4 ns
– 2.4 ns
– 3.0 ns
– 4.2 ns
– 3.9 – 5.3 ns
– 4.0 – 5.3 ns
– 3.6 – 4.6 ns
– 5.0 – 5.8 ns
– 5.0
– 0.4
– 6.3 ns
– 1.0 ns
0.1 – 0.5 – ns
4.5 – 5.8 – ns
– 2.3 – 2.5 ns
– 4.9
– 3.9
– 6.2 ns
– 4.5 ns
– 5.4 – 7.2 ns
2.9 4.0 3.5 4.7 ns
– 1.0
– 0.0
– 1.0 ns
– 0.0 ns
Table 2-0036A/1032E
7