1048C Datasheet, PDF (8/12 Pages) Lattice Semiconductor – In-System Programmable High Density PLD

Specifications ispLSI 1048C/883
ispLSI 1048C/883 Timing Model
I/O Cell
GRP
Ded. In
I/O Pin
(Input)
#59
#30
I/O Reg Bypass
#24
Input
D ^Register Q
RST
#25 - 29
Reset
GRP 4
#32
GRP
Loading
Delay
#31, 33,
34, 35
Feedback
GLB
4 PT Bypass
#36
20 PT
XOR Delays
#37, 38, 39
#59
GLB Reg Bypass
#40
GLB Reg
Delay
D
Q
RST
#41, 42,
43, 44
ORP
I/O Cell
ORP Bypass
#49
ORP
Delay
#48
#50
I/O Pin
(Output)
#51, 52
Y1,2,3
Clock
Distribution
#55, 56,
57, 58
Control _RE
PTs _OE
#45, 46, CK
47
#54
Y0
#53
GOE0, 1
0491A/48
Derivations of tsu, th and tco from the Product Term Clock¹
tsu = Logic + Reg su - Clock (min)
= (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min))
= (#24 + #32 + #38) + (#41) - (#24 + #32 + #47)
8.0 ns = (4.3 + 6.7 + 7.5) + (3.9) - (4.3 + 6.7 + 3.4)
th = Clock (max) + Reg h - Logic
= (tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor)
= (#24 + #32 + #47) + (#42) - (#24 + #32 + #38 )
8.0 ns = (4.3 + 6.7 + 8.2) + (7.3) - (4.3 + 6.7 + 7.5)
tco = Clock (max) + Reg co + Output
= (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob)
= (#24 + #32 + #47) + (#43) + (#48 + #50)
32.8 ns = (4.3 + 6.7 + 8.2) + (7.3) + (3.4 + 2.9)
Derivations of tsu, th and tco from the Clock GLB¹
tsu = Logic + Reg su - Clock (min)
= (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tgy0(min) + tgco + tgcp(min))
= (#24 + #32 + #38) + (#41) - (#54 + #43 + #56)
10.1 ns= (4.3 + 6.7 + 7.5) + (3.9) - (7.4 + 2.3 + 2.6)
th = Clock (max) + Reg h - Logic
= (tgy0(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor)
= (#54 + #43 + #56) + (#42) - (#24 + #32 + #38)
6.1 ns = (7.4 + 2.3 + 7.6) + (7.3) - (4.3 + 6.7 + 7.5)
tco = Clock (max) + Reg co + Output
= (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob)
= (#54 + #43 + #56) + (#43) + (#48 + #50)
30.9 ns = (7.4 + 2.3 + 7.6) + (7.3) + (3.4 + 2.9)
1. Calculations are based upon timing specifications for the ispLSI 1048C-50
8