1048C Datasheet, PDF(2/12 Page) Lattice Semiconductor – In-System Programmable High Density PLD

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1048C Datasheet, PDF (2/12 Pages) Lattice Semiconductor – In-System Programmable High Density PLD

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Specifications ispLSI 1048C/883

Functional Block Diagram

Figure 1. ispLSI 1048C/883 Functional Block Diagram

RESET

GOE0

GOE1

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

SDI/IN 0

MODE/IN 1

ispEN

I/O I/O I/O I/O I/O I/O I/OI/O I/O I/O I/O I/O I/O I/O I/O I/O IN IN

95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 11 10

I/O I/O I/O I/O I/O I/O I/OI/O I/O I/O I/O I/O I/O I/O I/O I/O IN IN

79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 9 8

Generic

Logic Blocks

(GLBs)

Input Bus

Output Routing Pool (ORP)

F7 F6 F5 F4 F3 F2 F1 F0

Input Bus

Output Routing Pool (ORP)

E7 E6 E5 E4 E3 E2 E1 E0

Megablock

Global

Routing

Pool

(GRP)

B0 B1 B2 B3 B4 B5 B6 B7

Output Routing Pool (ORP)

Input Bus

C0 C1 C2 C3 C4 C5 C6 C7

Output Routing Pool (ORP)

Input Bus

Clock

Distribution

Network

CLK 0

CLK 1

CLK 2

IOCLK 0

IOCLK 1

IN 7

IN 6

I/O 63

I/O 62

I/O 61

I/O 60

I/O 59

I/O 58

I/O 57

I/O 56

I/O 55

I/O 54

I/O 53

I/O 52

I/O 51

I/O 50

I/O 49

I/O 48

IN2 SDO/ I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

IN3 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

IN SCLK/ I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

4 IN 5 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

YYYY

0123

0139F(2)-48B-isp

The device also has a 96 I/O cells, each of which is

directly connected to an I/O pin. Each I/O cell can be

individually programmed to be a combinatorial input,

registered input, latched input, output or bi-directional

I/O pin with 3-state control. Additionally, all outputs have

selectable polarity, active high or active low. The signal

voltage levels are TTL-compatible, and the output drivers

can source 4 mA or sink 8 mA.

Eight GLBs, 16 I/O cells, two dedicated inputs and one

ORP are connected together to make a Megablock as

shown in figure 1. The outputs of the eight GLBs are

connected to a set of 16 universal I/O cells by the ORP.

Each ispLSI 1048C/883 device contains six Megablocks.

The GRP has, as its inputs, the outputs from all of the

GLBs and all of the inputs from the bi-directional I/O cells.

All of these signals are made available to the inputs of the

GLBs. Delays through the GRP have been equalized to

minimize timing skew.

Clocks in the ispLSI 1048C/883 device are selected

using the Clock Distribution Network. Four dedicated

clock pins (Y0, Y1, Y2 and Y3) are brought into the

distribution network, and five clock outputs (CLK 0, CLK

1, CLK 2, IOCLK 0 and IOCLK 1) are provided to route

clocks to the GLBs and I/O cells. The Clock Distribution

Network can also be driven from a special clock GLB (D0

on the ispLSI 1048C/883 device). The logic of this GLB

allows the user to create an internal clock from a combi-

nation of internal signals.

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