1048C Datasheet, PDF (4/12 Pages) Lattice Semiconductor – In-System Programmable High Density PLD

Specifications ispLSI 1048C/883
Switching Test Conditions
Input Pulse Levels
GND to 3.0V
Figure 2. Test Load
Input Rise and Fall Time
≤ 3ns 10% to 90%
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
1.5V
Output Load
See figure 2
3-state levels are measured 0.5V from steady-state
active level.
Table 2- 0003
Device
Output
+ 5V
R1
R2
Test
Point
CL*
Output Load Conditions (see figure 2)
Test Condition
A
B Active High
Active Low
Active High to Z
C at V_OH - 0.5V
Active Low to Z
at V + 0.5V
OL
R1
470Ω
∞
470Ω
∞
470Ω
R2
390Ω
390Ω
390Ω
390Ω
390Ω
CL
35pF
35pF
35pF
5pF
5pF
Table 2- 0004A
*CL includes Test Fixture and Probe Capacitance.
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL
VOL
VOH
IIL
IIH
IIL-isp
IIL-PU
IOS¹
ICC^2,4
PARAMETER
Output Low Voltage
Output High Voltage
Input or I/O Low Leakage Current
Input or I/O High Leakage Current
isp Input Low Leakage Current
I/O Active Pull-Up Current
Output Short Circuit Current
Operating Power Supply Current
CONDITION
I_OL =8 mA
I_OH =-4 mA
0V ≤ V_IN ≤ V_IL (MAX.)
3.5V ≤ V_IN ≤ V_CC
0V ≤ V_IN ≤ V_IL (MAX.)
0V ≤ V_IN ≤ V_IL
V_CC = 5V, V_OUT = 0.5V
V_IL = 0.5V, V_IH = 3.0V
f_TOGGLE = 1 MHz
MIN.
–
2.4
–
–
–
–
–
–
TYP. ³ MAX.
–
0.4
–
–
–
-10
–
10
– -150
– -150
– -200
165 260
UNITS
V
V
µA
µA
µA
µA
mA
mA
1. One output at a time for a maximum duration of one second. V_out = 0.5V was selected to avoid test problems by tester ground
degradation. Characterized but not 100% tested.
2. Measured using twelve 16-bit counters.
3. Typical values are at V = 5V and T = 25^oC.
CC
A
4. Maximum I_CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption sec-
tion of this datasheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum
I_CC.
0007A-48C mil
4