1048C Datasheet, PDF (7/12 Pages) Lattice Semiconductor – In-System Programmable High Density PLD

Specifications ispLSI 1048C/883
Internal Timing Parameters¹
PARAMETER #² DESCRIPTION
Outputs
tob
50 Output Buffer Delay
toen
51 I/O Cell OE to Output Enabled
todis
52 I/O Cell OE to Output Disabled
tgoe
53 Global OE
Clocks
tgy0
54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
tgy1/2
55 Clock Delay, Y1 or Y2 to Global GLB Clock Line
tgcp
56 Clock Delay, Clock GLB to Global GLB Clock Line
tioy2/3
57 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line
tiocp
58 Clock Delay, Clock GLB to I/O Cell Global Clock Line
Global Reset
tgr
59 Global Reset to GLB and I/O Registers
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
-50
UNITS
MIN. MAX.
– 2.9 ns
– ^{6.9 ns}
– ^{6.9 ns}
– ^{13.6 ns}
7.4 7.4 ^ns
6.1 8.7 ^ns
2.6 7.6 ns
6.1 8.7 ns
2.6 7.6 ^ns
– 11.4 ^ns
Table 2- 0037-48C/50mil
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