1048C Datasheet, PDF (5/12 Pages) Lattice Semiconductor – In-System Programmable High Density PLD

Specifications ispLSI 1048C/883
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER
TEST ⁴
COND.
#²
DESCRIPTION¹
tpd1
tpd2
fmax (Int.)
fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
twl
tsu3
th3
A 1 Data Propagation Delay, 4PT bypass, ORP bypass
A 2 Data Propagation Delay
A 3 Clock Frequency with Internal Feedback³
–
4
Clock
Frequency
with
External
Feedback
( _tsu2
1
+
) _tco1
–
5
Clock
Frequency,
Max
Toggle
(
1
twh + tw1
)
– 6 GLB Reg. Setup Time before Clock, 4PT bypass
A 7 GLB Reg. Clock to Output Delay, ORP bypass
– 8 GLB Reg. Hold Time after Clock, 4 PT bypass
– 9 GLB Reg. Setup Time before Clock
– 10 GLB Reg. Clock to Output Delay
– 11 GLB Reg. Hold Time after Clock
A 12 Ext. Reset Pin to Output Delay
– 13 Ext. Reset Pulse Duration
B 14 Input to Output Enable
C 15 Input to Output Disable
B 16 Global OE Output Enable
C 17 Global OE Output Disable
– 20 Ext. Sync. Clock Pulse Duration, High
– 21 Ext. Sync. Clock Pulse Duration, Low
– 22 I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3)
– 23 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-Bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
-50
UNITS
MIN. MAX.
– 22.0 ns
– 26.0 ns
50.3 – MHz
34.5 – MHz
58.8 – MHz
13.0 – ns
– 14.0 ns
0 – ns
15.0 – ns
– 16.0 ns
0 – ns
– 20.5 ns
13.5 – ns
– 27.5 ns
– 27.5 ns
– 20.5 ns
– 20.5 ns
8.5 – ns
8.5 – ns
3.0 – ns
9.0 – ns
Table 2- 0030-48C/50 mil
5