1048C Datasheet, PDF (6/12 Pages) Lattice Semiconductor – In-System Programmable High Density PLD

Specifications ispLSI 1048C/883
Internal Timing Parameters¹
PARAMETER #² DESCRIPTION
Inputs
tiobp
tiolat
tiosu
tioh
tioco
tior
tdin
GRP
tgrp1
tgrp4
tgrp8
tgrp16
tgrp48
GLB
t4ptbp
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgro
tptre
tptoe
tptck
ORP
torp
torpbp
24 I/O Register Bypass
25 I/O Latch Delay
26 I/O Register Setup Time before Clock
27 I/O Register Hold Time after Clock
28 I/O Register Clock to Out Delay
29 I/O Register Reset to Out Delay
30 Dedicated Input Delay
31 GRP Delay, 1 GLB Load
32 GRP Delay, 4 GLB Loads
33 GRP Delay, 8 GLB Loads
34 GRP Delay, 16 GLB Loads
35 GRP Delay, 48 GLB Loads
36 4 Product Term Bypass Path Delay
37 1 Product Term/XOR Path Delay
38 20 Product Term/XOR Path Delay
39 XOR Adjacent Path Delay³
40 GLB Register Bypass Delay
41 GLB Register Setup Time before Clock
42 GLB Register Hold Time after Clock
43 GLB Register Clock to Output Delay
44 GLB Register Reset to Output Delay
45 GLB Product Term Reset to Register Delay
46 GLB Product Term Output Enable to I/O Cell Delay
47 GLB Product Term Clock Delay
48 ORP Delay
49 ORP Bypass Delay
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
-50
UNITS
MIN. MAX.
– 4.3 ns
– 5.5 ns
9.1 – ns
0.3 – ns
– 4.6 ns
– 5.1 ns
– 7.4 ns
– 6.2 ns
– 6.7 ns
– 8.0 ns
– 10.5 ns
– 22.7 ns
– 5.5 ns
– 6.7 ns
– 7.5 ns
– 8.9 ns
– 1.2 ns
3.9 – ns
7.3 – ns
– 2.3 ns
– 2.8 ns
– 11.1 ns
– 9.6 ns
3.4 8.2 ns
– 3.4 ns
– 1.4 ns
Table 2- 0036-48C/50MIL
6