1048C Datasheet, PDF (10/12 Pages) Lattice Semiconductor – In-System Programmable High Density PLD

Specifications ispLSI 1048C/883
Pin Description
NAME
CPGA PIN NUMBERS
DESCRIPTION
I/O 0 - I/O 5
I/O 6 - I/O 11
I/O 12 - I/O 17
I/O 18 - I/O 23
I/O 24 - I/O 29
I/O 30 - I/O 35
I/O 36 - I/O 41
I/O 42 - I/O 47
I/O 48 - I/O 53
I/O 54 - I/O 59
I/O 60 - I/O 65
I/O 66 - I/O 71
I/O 72 - I/O 77
I/O 78 - I/O 83
I/O 84 - I/O 89
I/O 90 - I/O 95
GOE0, GOE1
J2, J3, K1, L1, K2, M1,
L2, K3, N1, M2, L3, P1,
M3, P2, N3, M4, P3, N4,
P4, M5, N5, P5, M6, N6,
N9, M9, P10, P11, N10, P12,
N11, M10, P13, N12, M11, P14,
M12, N14, M13, L12, M14, L13,
L14, K12, K13, K14, J12, J13,
F13, F12, E14, D14, E13, C14,
D13, E12, B14, C13, D12, A14,
C12, A13, B12, C11, A12, B11,
A11, C10, B10, A10, C9, B9,
B6, C6, A5, A4, B5, A3,
B4, C5, A2, B3, C4, A1,
C3, B1, C2, D3, C1, D2,
D1, E3, E2, E1, F3, F2
Input/Output Pins - These are the general purpose I/O pins used
by the logic array.
N13, B7,
Global output enables for all I/Os.
IN 2, IN 4
IN 6 - IN 11
P7, P9
Dedicated input pins to the device.
F14, A9, A8, A7, A6, F1
ispEN
H2
SDI/IN 0¹
J1
MODE/IN 1¹
P6
SDO/IN 3¹
P8
SCLK/IN 5¹
J14
Input – Dedicated in-system programming enable input pin. This
pin is brought low to enable the programming mode. The MODE,
SDI, SDO and SCLK options become active.
Input – This pin performs two functions. It is a dedicated input pin
when ispEN is logic high. When ispEN is logic low, it functions as
an input pin to load programming data into the device. SDI/IN 0
also is used as one of the two control pins for the isp state machine.
Input – This pin performs two functions. It is a dedicated input pin
when ispEN is logic high. When ispEN is logic low, it functions as
a pin to control the operation of the isp state machine.
Input/Output – This pin performs two functions. It is a dedicated
input pin when ispEN is logic high. When ispEN is logic low, it
functions as an output pin to read serial shift register data.
Input – This pin performs two functions. It is a dedicated input
when ispEN is logic high. When ispEN is logic low, it functions as
a clock pin for the Serial Shift Register.
RESET
H1
Y0
G1
Y1
G14
Y2
H13
Y3
H14
Active Low (0) Reset pin which resets all of the GLB and I/O
registers in the device.
Dedicated Clock input. This clock input is connected to one of the
clock inputs of all of the GLBs on the device.
Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on
the device.
Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB and/
or any I/O cell on the device.
Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any I/O cell on
the device.
GND
VCC
B2, B8, B13, C8, H3, H12,
M8, N2, N8
C7, G2, G3, G12, G13, M7,
N7
1. Pins have dual function capability.
Ground (GND)
V
CC
Table 2- 0002C-48C/CPGA
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