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PALCE20V8 Datasheet, PDF (4/27 Pages) Advanced Micro Devices – EE CMOS 24-Pin Universal Programmable Array Logic | |||
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CONFIGURATION OPTIONS
Each macrocell can be conï¬gured as one of the following: registered output, combinatorial
output, combinatorial I/O or dedicated input. In the registered output conï¬guration, the output
buffer is enabled by the OE pin. In the combinatorial conï¬guration, the buffer is either controlled
by a product term or always enabled. In the dedicated input conï¬guration, the buffer is always
disabled. A macrocell conï¬gured as a dedicated input derives the input signal from an adjacent
I/O.
The macrocell conï¬gurations are controlled by the conï¬guration control word. It contains 2
global bits (SG0 and SG1) and 16 local bits (SL00 through SL07 and SL10 through SL17). SG0
determines whether registers will be allowed. SG1 determines whether the PALCE20V8 will
emulate a PAL20R8 family or a combinatorial device. Within each macrocell, SL0x, in conjunction
with SG1, selects the conï¬guration of the macrocell and SL1x sets the output as either active low
or active high.
The conï¬guration bits work by acting as control inputs for the multiplexers in the macrocell.
There are four multiplexers: a product term input, an enable select, an output select, and a
feedback select multiplexer. SG1 and SL0x are the control signals for all four multiplexers. In MC0
and MC7, SG0 replaces SG1 on the feedback multiplexer.
These conï¬gurations are summarized in Table 1 and illustrated in Figure 2.
If the PALCE20V8 is conï¬gured as a combinatorial device, the CLK and OE pins may be available
as inputs to the array. If the device is conï¬gured with registers, the CLK and OE pins cannot be
used as data inputs.
Registered Output Conï¬guration
The control bit settings are SG0 = 0, SG1 = 1 and SL0x = 0. There is only one registered
conï¬guration. All eight product terms are available as inputs to the OR gate. Data polarity is
determined by SL1x. SL1x is an input to the exclusive-OR gate which is the D input to the ï¬ip-
ï¬op. SL1x is programmed as 1 for inverted output or 0 for non-inverted output. The ï¬ip-ï¬op is
loaded on the LOW-to-HIGH transition of CLK. The feedback path is from Q on the register. The
output buffer is enabled by OE.
Combinatorial Conï¬gurations
The PALCE20V8 has three combinatorial output conï¬gurations: dedicated output in a non-
registered device, I/O in a non-registered device and I/O in a registered device.
Dedicated Output in a Non-Registered Device
The control settings are SG0 = 1, SG1 = 0, and SL0x = 0. All eight product terms are available to
the OR gate. Although the macrocell is a dedicated output, the feedback is used, with the
exception of pins 18(21) and 19(23). Pins 18(21) and 19(23) do not use feedback in this mode.
Note:
1. The pin number without parentheses refers to the SKINNY DIP package. The pin number in parentheses refers to the PLCC
package.
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PALCE20V8 Family
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