PALCE20V8 Datasheet, PDF(26/27 Page) Advanced Micro Devices – EE CMOS 24-Pin Universal Programmable Array Logic

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PALCE20V8 Datasheet, PDF (26/27 Pages) Advanced Micro Devices – EE CMOS 24-Pin Universal Programmable Array Logic

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CONNECTION DIAGRAMS

Top View

SKINNYDIP

CLK/I0 1

I1 2

I2 3

I3 4

I4 5

I5 6

I6 7

I7 8

I8 9

I9 10

I10 11

GND 12

Note:

Pin 1 is marked for orientation.

VCC

I13

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0

I12

OE/I11

16491E-16

PLCC

4 3 2 1 28 27 26

I3 5

I4 6

I5 7

NC 8

25 I/O6

24 I/O5

23 I/O4

22 GND/NC *

I6 9

21 I/O3

I7 10

20 I/O2

I8 11

19 I/O1

12 13 14 15 16 17 18

16491E-17

PIN DESIGNATIONS

CLK = Clock

GND = Ground

= Input

I/O = Input/Output

NC = No Connect

OE = Output Enable

VCC = Supply Voltage

PALCE20V8 Family

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