PALCE20V8 Datasheet, PDF (24/27 Pages) Advanced Micro Devices – EE CMOS 24-Pin Universal Programmable Array Logic

POWER-UP RESET
The PALCE20V8 has been designed with the capability to reset during system power-up.
Following power-up, all flip-flops will be reset to LOW. The output state will be HIGH
independent of the logic polarity. This feature provides extra flexibility to the designer and is
especially valuable in simplifying state machine initialization. A timing diagram and parameter
table are shown below. Due to the synchronous operation of the power-up reset and the wide
range of ways V_CC can rise to its steady state, two conditions are required to ensure a valid
power-up reset. These conditions are:
x The V_CC rise must be monotonic.
x Following reset, the clock input must not be driven from LOW to HIGH until all applicable input
and feedback setup times are met.
Parameter Symbol
t_PR
t_S
t_WL
Parameter Descriptions
Power-Up Reset Time
Input or Feedback Setup Time
Clock Width LOW
Min
Max
Unit
1000
ns
See Switching Characteristics
4V
V_CC
Power
t_PR
Registered
Output
t_S
Clock
t_WL
Figure 2. Power-Up Reset Waveform
16491E-15
24
PALCE20V8 Family