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PALCE20V8 Datasheet, PDF (1/27 Pages) Advanced Micro Devices – EE CMOS 24-Pin Universal Programmable Array Logic | |||
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COM'L: H-5/7/10/15/25, Q-10/15/25 IND: H-15/25, Q-20/25
PALCE20V8 Family
EE CMOS 24-Pin Universal
Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
x Pin and function compatible with all PAL® 20V8 devices
x Electrically erasable CMOS technology provides reconï¬gurable logic and full testability
x High-speed CMOS technology
â 5-ns propagation delay for â-5â version
â 7.5-ns propagation delay for â-7â version
x Direct plug-in replacement for a wide range of 24-pin PAL devices
x Programmable enable/disable control
x Outputs individually programmable as registered or combinatorial
x Peripheral Component Interconnect (PCI) compliant
x Preloadable output registers for testability
x Automatic register reset on power-up
x Cost-effective 24-pin plastic SKINNY DIP and 28-pin PLCC packages
x Extensive third-party software and programmer support
x Fully tested for 100% programming and functional yields and high reliability
x Programmable output polarity
x 5-ns version utilizes a split leadframe for improved performance
GENERAL DESCRIPTION
The PALCE20V8 is an advanced PAL device built with low-power, high-speed, electrically-
erasable CMOS technology. Its macrocells provide a universal device architecture. The
PALCE20V8 is fully compatible with the GAL20V8 and can directly replace PAL20R8 series
devices and most 24-pin combinatorial PAL devices.
Device logic is automatically conï¬gured according to the userâs design speciï¬cation. A design is
implemented using any of a number of popular design software packages, allowing automatic
creation of a programming ï¬le based on Boolean or state equations. Design software also veriï¬es
the design and can provide test vectors for the ï¬nished device. Programming can be
accomplished on standard PAL device programmers.
The PALCE20V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to
implement complex logic functions easily and efï¬ciently. Multiple levels of combinatorial logic
can always be reduced to sum-of-products form, taking advantage of the very wide input gates
available in PAL devices. The equations are programmed into the device through ï¬oating-gate
cells in the AND logic array that can be erased electrically.
Publication# 16491 Rev: E
Amendment/0
Issue Date: November 1998
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