PALCE20V8 Datasheet, PDF (2/27 Pages) Advanced Micro Devices – EE CMOS 24-Pin Universal Programmable Array Logic

The fixed OR array allows up to eight data product terms per output for logic functions. The
sum of these products feeds the output macrocell. Each macrocell can be programmed as
registered or combinatorial with an active-high or active-low output. The output configuration
is determined by two global bits and one local bit controlling four multiplexers in each
macrocell.
BLOCK DIAGRAM
I₁ – I₁₀
CLK/I₀
10
Programmable AND Array
40 x 64
Input
Mux.
MACRO
MC₀
MACRO
MC₁
MACRO
MC₂
MACRO
MC₃
MACRO
MC₄
MACRO
MC₅
MACRO
MC₆
MACRO
MC₇
Input
Mux.
OE/I₁₁ I₁₂
I/O₀
I/O₁
I/O₂
I/O₃
I/O₄
I/O₅
I/O₆
I/O₇
I₁₃
16491E
FUNCTIONAL DESCRIPTION
The PALCE20V8 is a universal PAL device. It has eight independently configurable macrocells
(MC₀-MC₇). Each macrocell can be configured as a registered output, combinatorial output,
combinatorial I/O, or dedicated input. The programming matrix implements a programmable
AND logic array, which drives a fixed OR logic array. Buffers for device inputs have
complementary outputs to provide user-programmable input signal polarity. Pins 1 and 13 serve
either as array inputs or as clock (CLK) and output enable (OE) for all flip-flops.
Unused input pins should be tied directly to V_CC or GND. Product terms with all bits
unprogrammed (disconnected) assume the logical HIGH state, and product terms with both true
and complement of any input signal connected assume a logical LOW state.
The programmable functions on the PALCE20V8 are automatically configured from the user’s
design specification, which can be in a number of formats. The design specification is processed
2
PALCE20V8 Family