IS61WV5128ALL Datasheet, PDF (9/25 Pages) Integrated Silicon Solution, Inc – 512K x 8 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM

IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
READ CYCLE SWITCHING CHARACTERISTICS⁽¹⁾ (Over Operating Range)

-8
Symbol Parameter Min. Max.
-10
Min. Max. Unit
trc
Read Cycle Time 8 —
10 — ns
taa
Address Access Time — 8
— 10 ns
toha
Output Hold Time 2.0 —
2.0 — ns
tace
CE Access Time — 8
— 10 ns
tdoe
OE Access Time — 4.5
— 4.5 ns
thzoe⁽²⁾
OE to High-Z Output —
3
— 4 ns
tlzoe⁽²⁾
OE to Low-Z Output 0
—
0 — ns
thzce⁽²
CE to High-Z Output 0
3
0 4 ns
tlzce⁽²⁾
CE to Low-Z Output 3
—
3 — ns
tpu
Power Up Time 0 —
0 — ns
tpd
Power Down Time — 8
— 10 ns
Notes:
1.  Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output load-
ing specified in Figure 1.
2.  Tested with the load in Figure 2.Transition is measured ±500 mV from steady-state voltage.
Integrated Silicon Solution, Inc. — www.issi.com
9
Rev.  I
08/10/09